- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373771 > Z8S18006PSC (ZiLOG, Inc.) CAP 1000PF 100V 5% NP0(C0G) DIP-2 TUBE PDF資料下載
參數(shù)資料
| 型號： | Z8S18006PSC |
| 廠商： | ZiLOG, Inc. |
| 元件分類： | 微處理器 |
| 英文描述： | CAP 1000PF 100V 5% NP0(C0G) DIP-2 TUBE |
| 中文描述： | 強化Z180微處理器 |
| 文件頁數(shù)： | 57/70頁 |
| 文件大?。?/td> | 387K |
| 代理商： | Z8S18006PSC |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁當前第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
DS971800401
P R E L I M I N A R Y
1-57
1
Table 12 shows all DMA transfer mode combinations of
DM0, DM1, SM0, and SM1. Since I/O to/from I/O transfers
are not implemented, 12 combinations are available.
MMOD: Memory Mode Channel 0 (bit).
When channel 0
is configured for memory to/from memory transfers there is
no Request Handshake signal to control the transfer tim-
ing. Instead, two automatic transfer timing modes are se-
lectable: burst (MMOD = 1) and cycle steal (MMOD = 0).
For burst memory to/from memory transfers, the DMAC
takes control of the bus continuously until the DMA transfer
completes (as shown by the byte count register = 0). In cy-
cle steal mode, the CPU is given a cycle for each DMA
byte transfer cycle until the transfer is completed.
For channel 0 DMA with I/O source or destination, the se-
lected Request signal times the transfer and thus MMOD
is ignored. MMOD is cleared to 0 during RESET.
Table 12. Transfer Mode Combinations
Address
DM1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Note:
* Includes memory mapped I/O.
DM0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
SM1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
SM0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
Transfer Mode
Memory
→
Memory
Memory
→
Memory
Memory*
→
Memory
I/O
→
Memory
Memory
→
Memory
Memory
→
Memory
Memory*
→
Memory
I/O
→
Memory
Memory
→
Memory*
Memory
→
Memory*
Reserved
Reserved
Memory
→
I/O
Memory I/O
Reserved
Reserved
Increment/Decrement
SAR0+1, DAR0+1
SAR0–1, DAR0+1
SAR0 fixed, DAR0+1
SAR0 fixed, DAR0+1
SAR0+1, DAR0–1
SAR0–1, DAR0–1
SAR0 fixed, DAR0–1
SAR0 fixed, DAR0–1
SAR0+1, DAR0 fixed
SAR0–1, DAR0 fixed
SAR0+1, DAR0 fixed
SAR0–1, DAR0 fixed
相關PDF資料 |
PDF描述 |
|---|---|
| Z90102 | CAP 560PF 100V 10% X7R AXIAL BULK R-MIL-PRF-39014 |
| Z90103 | CAP 680PF 100V 10% X7R AXIAL BULK R-MIL-PRF-39014 |
| Z90104 | CAP 820PF 100V 10% X7R AXIAL BULK R-MIL-PRF-39014 |
| Z90110 | CAP 1000PF 100V 10% X7R AXIAL BULK R-MIL-PRF-39014 |
| Z90120 | CAP 1000PF 100V 20% X7R AXIAL BULK R-MIL-PRF-39014 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| Z8S18006VEC | 制造商:ZILOG 制造商全稱:ZILOG 功能描述:ENHANCED Z180 MICROPROCESSOR |
| Z8S18006VSC | 制造商:ZILOG 制造商全稱:ZILOG 功能描述:ENHANCED Z180 MICROPROCESSOR |
| Z8S18008FEC | 制造商:ZILOG 制造商全稱:ZILOG 功能描述:ENHANCED Z180 MICROPROCESSOR |
| Z8S18008FSC | 制造商:ZILOG 制造商全稱:ZILOG 功能描述:ENHANCED Z180 MICROPROCESSOR |
| Z8S18008PEC | 制造商:ZILOG 制造商全稱:ZILOG 功能描述:ENHANCED Z180 MICROPROCESSOR |
發(fā)布緊急采購，3分鐘左右您將得到回復。