參數(shù)資料
型號: Z8S18006PSC
廠商: ZiLOG, Inc.
元件分類: 微處理器
英文描述: CAP 1000PF 100V 5% NP0(C0G) DIP-2 TUBE
中文描述: 強(qiáng)化Z180微處理器
文件頁數(shù): 56/70頁
文件大?。?/td> 387K
代理商: Z8S18006PSC
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
1-56
P R E L I M I N A R Y
DS971800401
DMA MODE REGISTER (DMODE).
DMODE is used to set the addressing and transfer mode
for channel 0.
Mnemonic DMODE
Address 31H
DM1, DM0: Destination Mode Channel 0 (bits 5,4)
spec-
ifies whether the destination for channel 0 transfers is
memory or I/O, and whether the address should be incre-
mented or decremented for each byte transferred. DM1
and DM0 are cleared to 0 during RESET.
SM1, SM0: Source Mode Channel 0 (bits 3, 2)
specifies
whether the source for channel 0 transfers is memory or
I/O, and whether the address should be incremented or
decremented for each byte transferred.
Figure 73. DMA Mode Register (DMODE: I/O Address = 31H)
Bit
DM1
DM0
7
6
5
4
3
2
1
0
R/W
R/W
SM1
SM0
MMOD
R/W
R/W
R/W
Table 10. Channel 0 Destination
Memory
DM1
0
0
1
1
DM0
0
1
0
1
Memory I/O
Memory
Memory
Memory
I/O
Increment/Decrement
+1
–1
fixed
fixed
Table 11. Channel 0 Source
Memory
SM1
0
0
1
1
SM0
0
1
0
1
Memory I/O
Memory
Memory
Memory
I/O
Increment/Decrement
+1
–1
fixed
fixed
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