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參數(shù)資料
| 型號(hào)： | ZL50018 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | 2 K Digital Switch with Enhanced Stratum 3 DPLL |
| 中文描述： | 2度數(shù)字交換機(jī)增強(qiáng)地層3數(shù)字鎖相環(huán) |
| 文件頁(yè)數(shù)： | 17/136頁(yè) |
| 文件大?。?/td> | 1448K |
| 代理商： | ZL50018 |
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ZL50018
Data Sheet
17
Zarlink Semiconductor Inc.
B10
155
FPi
ST-BUS/GCI-Bus
Schmitt-Triggered Input)
This pin accepts the frame pulse which stays active for 61 ns,
122 ns or 244 ns at the frame boundary. The frame pulse
frequency is 8 kHz.
The frame pulse associated with the
highest input or output
data
rate must be applied to this pin when the device is operating in
Divided Slave mode or Master mode. The exception is if the device
is operating in Master mode with loopback (i.e., CKi_LP is set in
the Control Register). In that case, this input must be tied high or
low externally.
When the device is operating in Multiplied Slave mode, the frame
pulse associated with the
highest
input
data rate must be applied
to this pin.
For all modes (except Master mode with loopback), if the data rate
is 16.384 Mbps, a 61 ns wide frame pulse must be used.
By default, the device accepts a negative frame pulse in ST-BUS
format, but it can accept a positive frame pulse instead if the
FPINP bit is set high in the Control Register (CR). It can accept a
GCI-formatted frame pulse by programming the FPINPOS bit in
the Control Register (CR) to high.
Frame
Pulse
Input
(5 V-Tolerant
B11
154
CKi
ST-BUS/GCI-Bus Clock Input (5 V-Tolerant Schmitt Triggered
Input)
This pin accepts a 4.096, 8.192 or 16.384 MHz clock.
The clock frequency associated with
twice the highest input or
output
data rate must be applied to this pin when the device is
operating in either Divided Slave mode or Master mode. The
exception is if the device is operating in Master mode with
loopback (i.e., CKi_LP is set in the Control Register). In that case,
this input must be tied high or low externally. The clock frequency
associated with
twice the highest input
data rate must be applied
to this pin when the device is operating in Multiplied Slave mode.
In all modes of operation (except Master mode with loopback),
when data is running at 16.384 Mbps, a 16.384 MHz clock must be
used. By default, the clock falling edge defines the input frame
boundary, but the device allows the clock rising edge to define the
frame boundary by programming the CKINP bit in the Control
Register (CR).
PBGA Pin
Number
LQFP Pin
Number
Pin Name
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ZL50018GAC | 2 K Digital Switch with Enhanced Stratum 3 DPLL |
| ZL50018QCC | 2 K Digital Switch with Enhanced Stratum 3 DPLL |
| ZL50019 | Enhanced 2 K Digital Switch with Stratum 4E DPLL |
| ZL50019GAC | Enhanced 2 K Digital Switch with Stratum 4E DPLL |
| ZL50019QCC | Enhanced 2 K Digital Switch with Stratum 4E DPLL |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZL50018_06 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:2 K Digital Switch with Enhanced Stratum 3 DPLL |
| ZL50018GAC | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 2K X 2K 1.8V/3.3V 256BGA - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC TDM SWITCH 2K-CH ENH 256PBGA 制造商:Microsemi Corporation 功能描述:IC TDM SWITCH 2K-CH ENH 256PBGA |
| ZL50018GAG2 | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 2K X 2K 1.8V/3.3V 256BGA - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC TDM SWITCH 2K-CH ENH 256PBGA 制造商:Microsemi Corporation 功能描述:IC TDM SWITCH 2K-CH ENH 256PBGA |
| ZL50018QCC | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 2K X 2K 1.8V/3.3V 256LQFP - Trays |
| ZL50018QCG1 | 制造商:Microsemi Corporation 功能描述:PB FREE 2K+ RATE CONVERSION AND S3 DPLL - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC TDM SWITCH 2K-CH ENH 256LQFP |
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