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參數(shù)資料
| 型號(hào)： | ZL50018 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | 2 K Digital Switch with Enhanced Stratum 3 DPLL |
| 中文描述： | 2度數(shù)字交換機(jī)增強(qiáng)地層3數(shù)字鎖相環(huán) |
| 文件頁(yè)數(shù)： | 44/136頁(yè) |
| 文件大?。?/td> | 1448K |
| 代理商： | ZL50018 |
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ZL50018
Data Sheet
44
Zarlink Semiconductor Inc.
14.0 Jitter Performance
14.1 Input Clock Cycle to Cycle Timing Variation Tolerance
The ZL50018 has an exceptional cycle to cycle timing variation tolerance of 20 ns. This allows the ZL50018
to synchronize off a low cost DPLL when it is in either Divided Slave mode or Multiplied Slave mode.
14.2 Input Jitter Acceptance
The input jitter acceptance is specified in standards as the minimum amount of jitter of a certain frequency on the
input clock that the DPLL must accept without making cycle slips or losing lock. The lower the jitter frequency, the
larger the jitter acceptance. For jitter frequencies below a tenth of the cut-off frequency of the DPLL's jitter transfer
function, it safely can be said that any provided input jitter will be followed by the DPLL. The maximum value of jitter
tolerance for the DPLL is
±
1023 UI
p-p
.
14.3 Jitter Transfer Function
The corner frequency (-3 dB) of the DPLL is programmable through LPF (bits 3 - 0) in the Bandwidth Control
Register (BWCR) from 0.475 Hz to 15.5 kHz, in 16 steps. Stratum 3 requires a corner frequency of maximally 3 Hz.
The default corner frequency is 1.9 Hz.
15.0 DPLL Specific Functions and Requirements
15.1 Lock Detector
To determine if the DPLL is locked to the input clock, a lock detector monitors the phase value output of the phase
detector, which represents the difference between input reference and output feedback clock. If the phase value is
below a certain threshold for a certain interval, the DPLL is pronounced locked to the input clock. The monitoring is
done in intervals of 4ms. The lock detector threshold and the interval are programmable by the user through the
Lock Detector Threshold Register (LDTR) and the Lock Detector Interval Register (LDIR) respectively. See
Table 36 on page 72 and Table 37 on page 72 for the bit descriptions of the Lock Detector Threshold Register
(LDTR) and Lock Detector Interval Register (LDIR) respectively. The value of the Lock Detector Threshold Register
(LDTR) should be programmed with respect to the maximum expected jitter frequency and amplitude on the
selected input references.
The lock status can be monitored through the Reference Change Status Register (RCSR). See Table 41 on
page 76 for the bit description of the Reference Change Status Register (RCSR).
15.2 Maximum Time Interval Error (MTIE)
Several standards require that the output clock of the DPLL may not move in phase more than a certain amount. In
order to meet those standards, a special circuit maintains the phase of the DPLL output clock during reference and
mode rearrangements. The total output phase change or Maximum Timing Interval Error (MTIE) during
rearrangements is less than 31 ns per rearrangement, exceeding Stratum 3 requirements. After a large number of
reference switches, the accumulated phase error can become significant, so it is recommended to use MTIE reset
in such situations, to realign outputs to the nearest edge of the selected reference. The MTIE reset can be
programmed by setting MTR (bit 7) in the Reference Change Control Register (RCCR), as described in Table 40 on
page 75.
15.3 Phase Alignment Speed (Phase Slope)
Besides total phase change, standards also require a certain rate of the phase change of the output clock. The
phase alignment speed is programmable by the user through a value in the Slew Rate Limit Register (SRLR) as
described in Table 38 on page 73. Stratum 3 requires that the phase alignment speed not exceed 81 ns per
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ZL50018GAC | 2 K Digital Switch with Enhanced Stratum 3 DPLL |
| ZL50018QCC | 2 K Digital Switch with Enhanced Stratum 3 DPLL |
| ZL50019 | Enhanced 2 K Digital Switch with Stratum 4E DPLL |
| ZL50019GAC | Enhanced 2 K Digital Switch with Stratum 4E DPLL |
| ZL50019QCC | Enhanced 2 K Digital Switch with Stratum 4E DPLL |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZL50018_06 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:2 K Digital Switch with Enhanced Stratum 3 DPLL |
| ZL50018GAC | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 2K X 2K 1.8V/3.3V 256BGA - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC TDM SWITCH 2K-CH ENH 256PBGA 制造商:Microsemi Corporation 功能描述:IC TDM SWITCH 2K-CH ENH 256PBGA |
| ZL50018GAG2 | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 2K X 2K 1.8V/3.3V 256BGA - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC TDM SWITCH 2K-CH ENH 256PBGA 制造商:Microsemi Corporation 功能描述:IC TDM SWITCH 2K-CH ENH 256PBGA |
| ZL50018QCC | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 2K X 2K 1.8V/3.3V 256LQFP - Trays |
| ZL50018QCG1 | 制造商:Microsemi Corporation 功能描述:PB FREE 2K+ RATE CONVERSION AND S3 DPLL - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC TDM SWITCH 2K-CH ENH 256LQFP |
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