參數(shù)資料
型號(hào): ZL50018
廠商: Zarlink Semiconductor Inc.
英文描述: 2 K Digital Switch with Enhanced Stratum 3 DPLL
中文描述: 2度數(shù)字交換機(jī)增強(qiáng)地層3數(shù)字鎖相環(huán)
文件頁數(shù): 79/136頁
文件大?。?/td> 1448K
代理商: ZL50018
ZL50018
Data Sheet
79
Zarlink Semiconductor Inc.
Bit
Name
Description
15 - 0
MFU15 - 0
Multiple-Period Far Upper Limit Bits:
Total binary value of these bits and the
MPFULRU register bits defines the far upper limit for the multiple period count of any
reference input,
minus 1
. The unit of the binary value is measured in 100 MHz clock
periods.
Note 1:
The default value represents far upper limit for all reference frequencies, which is +11.287 ppm (Stratum 3 compliant
value), regardless of the reference frequency.
Note 2:
The name ’upper’ is based on frequency.
Table 44 - Multi-period Far Upper Limit Register - Lower 16 Bits (MPFULRL)
Bit
Name
Description
15 - 0
MFU31 - 16
Multiple-Period Far Upper Limit Bits:
Total binary value of these bits and the
MPFULRL register bits defines the far upper limit for the multiple period count of any
reference input,
minus 1
. The unit of the binary value is measured in 100 MHz clock
periods.
Note 1:
The default value represents far upper limit for all reference frequencies, which is +11.287 ppm (Stratum 3 compliant
value), regardless of the reference frequency.
Note 2:
The name ’upper’ is based on frequency.
Table 45 - Multi-period Far Upper Limit Register - Upper 16 Bits (MPFULRU)
External Read/Write Address: 0050
H
Reset Value: 9DE8
H
(Note 1)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MFU
15
MFU
14
MFU
13
MFU
12
MFU
11
MFU
10
MFU
9
MFU
8
MFU
7
MFU
6
MFU
5
MFU
4
MFU
3
MFU
2
MFU
1
MFU
0
External Read/Write Address: 0051
H
Reset Value: 3B9A
H
(Note 1)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MFU
31
MFU
30
MFU
29
MFU
28
MFU
27
MFU
26
MFU
25
MFU
24
MFU
23
MFU
22
MFU
21
MFU
20
MFU
19
MFU
18
MFU
17
MFU
16
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