
PRODUCT SPECIFICATION
REVISION: ECR/ECN INFORMATION:
SHEET No.
EC No:
MG2007-0056
3
DATE:
2006 / 11 / 09
TITLE:
PRODUCT SPECIFICATION
HyperJack
TM 1000 PoE Module
85586 Series
41 of 58
DOCUMENT NUMBER:
CREATED / REVISED BY:
CHECKED BY:
APPROVED
PS-85586-001
S.Steinke
J.Hoennige
A. Vogt
TEMPLATE FILENAME:_PRODUCT_SPEC_X[SIZE_A4](V.1).DOC
3.3.3.2.
Write Cycle
Data write transfers to the HyperJack 1000 PoE Module consist of a 3-byte operation. The sequence in
this case would be to send a slave device address byte, followed by a write of the port/register address
and a write of the data byte for the addressed port. All bytes are followed by an acknowledge bit. The
sequence begins with a start sequence and ends with a stop condition.
The write cycle consists of the following steps 1 thru 9 and is also shown in Figure 16.
1.
Start Sequence (S)
2.
Device address field
3.
Write
4.
Acknowledge
5.
Register/Port address
6.
Acknowledge
7.
Data for device (TPS2384)
8.
Acknowledge
9.
Stop (P)
The IC interface and the port read/write registers are held in active reset until input voltage is within
specification and the internal POR timer has timed out.
3.3.3.3.
Start / Stop
The high-to-low transition of SDA while SCL is high defines the start condition. The low to high transition
of SDA while SCL is high defines the stop condition. The master device initiates all start and stop
conditions.
3.3.3.4.
Port / Register Sequence
After the chip address cycle the module accepts eight bits of port/register select data as defined in table 4.
The SCL line high-to-low transition after eighth data bit then latches the selection of the appropriate
internal register for the follow-on data read or write operation. After latching the eight bit data field, the
module pulls the SDA line low for one clock cycle (acknowledge pulse).
3.3.3.5.
Write Sequence
For a data write sequence, after the port/register access cycle the module accepts the eight bits of
data. The data is latched into the previously selected write register, and the module generates a data
acknowledge pulse by pulling the SDA line low for one clock cycle. Common register functions act on
all ports simultaneously. Per port registers are specific to the target port only. To reset the interface, the
host or master subsequently generates a stop bit by releasing the SDA line during the clock-high
portion of an SCL pulse. Common register functions act on all ports simultaneously. Per port registers
are specific to the target port only.
3.3.3.6.
Read Sequence
For a data read sequence, after the register acknowledge bit, the master device generates a stop
condition. This is followed by a second start condition and retransmitting the device address as described
above. For this cycle, however, the R/W bit is set to a 1 to signal the read operation. The module again
responds with an acknowledge pulse. The address acknowledge is again followed by sequentially
presenting each of the eight data bits on the SDA line (MSB first), to be read by the host device on the
rising edges of SCL. After the eight bits are transmitted, the host acknowledges by pulling the SDA line
high for one clock pulse. The completed data transfer is terminated with the host generating a stop
condition.