參數(shù)資料
型號： 1893YI-10
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 網(wǎng)絡(luò)接口
英文描述： DATACOM, INTERFACE CIRCUIT, PQFP64
封裝： 10 X 10 MM, TQFP-64
文件頁數(shù)： 49/152頁
文件大?。?/td> 943K
代理商： 1893YI-10
ICS1893 Rev C 6/6/00
June, 2000
142
Chapter 10
DC and AC Operating Conditions
ICS1893 Data Sheet - Release
Copyright 2000, Integrated Circuit Systems, Inc.
All rights reserved.
10.5.16
100M Media Dependent Interface: Input-to-Carrier Assertion/De-Assertion
Table 10-23 lists the significant time periods for the 100M MDI input-to-carrier assertion/de-assertion. The
time periods consist of timings of signals on the following pins:
TP_RX (that is, TP_RXP and TP_RXN)
CRS
COL
Figure 10-17 shows the timing diagram for the time periods.
The IEEE maximum is 20 bit times.
The IEEE minimum is 13 bit times, and the maximum is 24 bit times.
Figure 10-17.
100M MDI Input to Carrier Assertion / De-Assertion Timing Diagram
Table 10-23.
100M MDI Input-to-Carrier Assertion/De-Assertion Timing
Time
Period
Parameter
Conditions
Min.
Typ.
Max.
Units
t1
First Bit of /J/ into TP_RX to CRS Assert
–
10
–
14
Bit times
t2
First Bit of /J/ into TP_RX while
Transmitting Data to COL Assert
Half-Duplex Mode
9
–
13
Bit times
t3
First Bit of /T/ into TP_RX to CRS
De-Assert
–
13
–
18
Bit times
t4
First Bit of /T/ Received into TP_RX to
COL De-Assert
Half-Duplex Mode
13
–
18
Bit times
t1
t2
t3
t4
First bit
First bit of /T/
Shown
unscrambled.
TP_RX
CRS
COL
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