參數(shù)資料
型號： 1893YI-10
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 網(wǎng)絡(luò)接口
英文描述： DATACOM, INTERFACE CIRCUIT, PQFP64
封裝： 10 X 10 MM, TQFP-64
文件頁數(shù)： 93/152頁
文件大?。?/td> 943K
代理商： 1893YI-10
Chapter 7
Functional Blocks
ICS1893 Rev C 6/6/00
June, 2000
45
ICS1893 - Release
Copyright 2000, Integrated Circuit Systems, Inc.
All rights reserved.
7.3.3
PCS/PMA Transmit Modules
Both the PCS and PMA sublayers have Transmit modules.
7.3.3.1
PCS Transmit Module
The ICS1893 PCS Transmit module accepts nibbles from the MAC/Repeater Interface and converts the
nibbles into 5-bit ‘code groups’(referred to here as ‘symbols’). In addition, the PCS Transmit module
performs a parallel-to-serial conversion on the symbols, and subsequently passes the resulting serial bit
stream to the PMA sublayer.
The first 16 nibbles of each MAC/Repeater Frame represent the Frame Preamble. The PCS replaces the
first two nibbles of the Frame Preamble with the Start-of-Stream Delimiter (SSD), that is, the symbols /J/K/.
After receipt of the last Frame nibble, detected when TX_EN = FALSE, the PCS appends to the end of the
Frame an End-of-Stream Delimiter (ESD), that is, the symbols /T/R/. (The ICS1893 PCS does not alter any
other data included within the Frame.)
The PCS Transmit module also performs collision detection. In compliance with the ISO/IEC specification,
when the transmission and reception of data occur simultaneously and the ICS1893 is in:
Half-duplex mode, the ICS1893 asserts the collision detection signal (COL).
Full-duplex mode, COL is always FALSE.
7.3.3.2
PMA Transmit Module
The ICS1893 PMA Transmit module accepts a serial bit stream from its PCS and converts the data into
NRZI format. Subsequently, the PMA passes the NRZI bit stream to the Twisted-Pair Physical Medium
Dependent (TP-PMD) sublayer.
The ICS1893 PMA Transmit module uses a digital PLL to synthesize a transmit clock from the Clock
Reference Interface. When the ICS1893 is configured for an interface that is:
10M MII (that is, 10Base-T), the TXCLK signal is 2.5 MHz
10M Serial Interface, the TXCLK signal is 10 MHz
Either of the following, the TXCLK signal (a buffered version of the REF_IN signal) is 25 MHz:
– 100M MII (that is, 100Base-TX)
– 100M Symbol Interface
Note:
1.
All of the TXCLK signals are derived from the REF_IN signal that goes to the digital PLL.
2.
For the MII, for both the 10Base-T and 100Base-TX modes, the clock that is generated synchronizes
all data transfers across the MII.
相關(guān)PDF資料
PDF描述
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