- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄293745 > 1893YI-10 (INTEGRATED DEVICE TECHNOLOGY INC) DATACOM, INTERFACE CIRCUIT, PQFP64 PDF資料下載
參數(shù)資料
| 型號： | 1893YI-10 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 網(wǎng)絡接口 |
| 英文描述： | DATACOM, INTERFACE CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, TQFP-64 |
| 文件頁數(shù)： | 94/152頁 |
| 文件大小： | 943K |
| 代理商： | 1893YI-10 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁當前第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁
ICS1893 Rev C 6/6/00
June, 2000
46
Chapter 7
Functional Blocks
ICS1893 Data Sheet - Release
Copyright 2000, Integrated Circuit Systems, Inc.
All rights reserved.
7.3.4
PCS/PMA Receive Modules
Both the PCS and PMA sublayers have Receive modules.
7.3.4.1
PCS Receive Module
The ICS1893 PCS Receive module accepts both a serial bit stream and a clock signal from the PMA
sublayer. The PCS Receive module converts the bit stream from a serial format to a parallel format and
then processes the data to detect the presence of a carrier.
When a link is in the idle state, the PCS Receive module receives IDLE symbols. (All bits are logic one.)
Upon receiving two non-contiguous zeros in the bit stream, the PCS Receive module examines the
ensuing bits and attempts to locate the Start-of-Stream Delimiter (SSD), that is, the /J/K/ symbols.
Upon verification of a valid SSD, the PCS Receive module substitutes the first two standard nibbles of a
Frame Preamble for the detected SSD. In addition, the PCS Receive module uses the SSD to begin
framing the ensuing data into 5-bit code symbols. The final PCS Receive module performs 4B/5B decoding
on the symbols and then synchronously passes the resulting nibbles to the MAC/Repeater Interface.
The Receive state machine continues to accept PMA data, convert it from serial to parallel format, frame it,
decode it, and pass it to the MAC/Repeater Interface. During this time, the Receive state machine
alternates between Receive and Data States. It continues this process until detecting one of the following:
An End-of-Stream Delimiter (ESD, that is, the /T/R/ symbols)
An error
A premature end (IDLEs)
Upon receipt of an ESD, the Receive state machine returns to the IDLE state without passing the ESD to
the MAC/Repeater Interface. Detection of an error forces the Receive state machine to assert the receive
error signal (RX_ER) and wait for the next symbol. If the ICS1893 Receive state machine detects a
premature end, it forces the assertion of the RX_ER signal, sets the Premature End bit (bit 17.5) to logic
one, and transitions to the IDLE State.
7.3.4.2
PMA Receive Modules
The ICS1893 has a PMA Receive module that provides the following functions:
NRZI Decoding
The Receive module performs the NRZI decoding on the serial bit stream received from the Twisted-Pair
Physical Medium Dependent (TP-PMD) sublayer. It converts the bit stream to a unipolar, positive, binary
format that the PMA subsequently passes to the PCS.
Receive Clock Recovery
The Receive Clock Recovery function consists of a phase-locked loop (PLL) that operates on the serial
data stream received from the PMD sublayer. This PLL automatically synchronizes itself to the clock
encoded in the serial data stream and then provides both a recovered clock and data stream to the PCS.
Link Monitoring
– The ICS1893’s PMA Link Monitoring function observes the Receive Clock PLL. If the Receive Clock
PLL cannot acquire ‘lock’on the serial data stream, it asserts an error signal. The status of this error
signal can be read in the QuickPoll Detailed Status Register’s PLL Lock Error bit (bit 17.9). This bit is
a latching high (LH) bit. (For more information on latching high and latching low bits, see Section
8.1.4.1, “Latching High Bits”and Section 8.1.4.2, “Latching Low Bits”.)
– In addition, the ICS1893’s PMA Link Monitor function continually audits the state of the connection
with the remote link partner. It asserts a receive channel error if a receive signal is not detected or if
a PLL Lock Error occurs. These errors, in turn, generate a link fault and force the link monitor
function to clear both the Status Register’s Link Status bit (bit 1.2) and the QuickPoll Detailed Status
Register’s Link Status bit (bit 17.0).
相關PDF資料 |
PDF描述 |
|---|---|
| 1894-40KLF | DATACOM, INTERFACE CIRCUIT, QCC40 |
| 1894-40KLFT | DATACOM, INTERFACE CIRCUIT, QCC40 |
| 1895230000 | 15 A, STRIP TERMINAL BLOCK, 2 ROWS, 2 DECKS |
| 18F-08P-241 | 8 CONTACT(S), CABLE MOUNT, MINI DIN CONNECTOR, PLUG |
| 18F-08P-244 | 8 CONTACT(S), CABLE MOUNT, MINI DIN CONNECTOR, PLUG |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 1893YI-10LF | 功能描述:以太網(wǎng) IC 3.3V 10/100 BASE TX INTEGRATED PHYCEIVER RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| 1893YI-10LFT | 功能描述:以太網(wǎng) IC 3.3V 10/100 BASE TX INTEGRATED PHYCEIVER RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| 1894 | 功能描述:支架與墊片 HEX .187X.625 ALUM RoHS:否 制造商:Schurter 類型:Transipillar Spacers 長度:16 m 螺紋大小:M4 外徑:10 mm 材料:Nylon with Steel 電鍍:Zinc |
| 1894# | 制造商:Fluke Electronics 功能描述:BNC (F)/BANANA PLUG 制造商:Pomona Electronics 功能描述: |
| 1894 | 制造商:Pomona Electronics 功能描述:ADAPTER BNC FEMALE-BANANA PLUG 制造商:Pomona Electronics 功能描述:ADAPTER, BNC FEMALE-BANANA PLUG |
發(fā)布緊急采購，3分鐘左右您將得到回復。