參數(shù)資料
型號: 1893YI-10
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 網(wǎng)絡接口
英文描述: DATACOM, INTERFACE CIRCUIT, PQFP64
封裝: 10 X 10 MM, TQFP-64
文件頁數(shù): 85/152頁
文件大?。?/td> 943K
代理商: 1893YI-10
ICS1893 Rev C 6/6/00
June, 2000
38
Chapter 7
Functional Blocks
ICS1893 Data Sheet - Release
Copyright 2000, Integrated Circuit Systems, Inc.
All rights reserved.
7.1
Functional Block: Media Independent Interface
All ICS1893 MII interface signals are fully compliant with the ISO/IEC 8802-3 standard. In addition, the
ICS1893 MIIs can support two data transfer rates: 25 MHz (for 100Base-TX operations) and 2.5 MHz (for
10Base-T operations).
The Media Independent Interface (MII) consists of two primary components:
1.
An interface between a MAC (Media Access Control sublayer) and the PHY (that is, the ICS1893). This
MAC-PHY part of the MII consists of three subcomponents:
a. A synchronous Transmit interface that includes the following signals:
(1) A data nibble, TXD[3:0]
(2) An error indicator, TXER
(3) A delimiter, TXEN
(4) A clock, TXCLK
b. A synchronous Receive interface that includes the followings signals:
(1) A data nibble, RXD[3:0]
(2) An error indicator, RXER
(3) A delimiter, RXDV
(4) A clock, RXCLK
c. A Media Status or Control interface that consists of a Carrier Sense signal (CRS) and a Collision
Detection signal (COL).
2.
An interface between the PHY (the ICS1893) and an STA (Station Management entity). The STA-PHY
part of the MII is a two-wire, Serial Management Interface that consists of the following:
a. A clock (MDC)
b. A synchronous, bi-directional data signal (MDIO) that provides an STA with access to the ICS1893
Management Register set
The ICS1893 Management Register set (discussed in Chapter 8, “Management Register Set”) consists of
the following:
Basic Management registers.
As defined in the ISO/IEC 8802-3 standard, these registers include the following:
– Control Register (register 0), which handles basic device configuration
– Status Register (register 1), which reports basic device capabilities and status
Extended Management registers.
As defined in the ISO/IEC 8802-3 standard, the ICS1893 supports Extended registers that provide
access to the Organizationally Unique Identifier and all auto-negotiation functionality.
ICS (Vendor-Specific) Management registers.
The ICS1893 provides vendor-specific registers for enhanced PHY operations. Among these is the
QuickPoll Detailed Status Register that provides a comprehensive and consolidated set of real-time PHY
information. Reading the QuickPoll register enables the MAC to obtain comprehensive status data with
a single register access.
相關(guān)PDF資料
PDF描述
1894-40KLF DATACOM, INTERFACE CIRCUIT, QCC40
1894-40KLFT DATACOM, INTERFACE CIRCUIT, QCC40
1895230000 15 A, STRIP TERMINAL BLOCK, 2 ROWS, 2 DECKS
18F-08P-241 8 CONTACT(S), CABLE MOUNT, MINI DIN CONNECTOR, PLUG
18F-08P-244 8 CONTACT(S), CABLE MOUNT, MINI DIN CONNECTOR, PLUG
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
1893YI-10LF 功能描述:以太網(wǎng) IC 3.3V 10/100 BASE TX INTEGRATED PHYCEIVER RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray
1893YI-10LFT 功能描述:以太網(wǎng) IC 3.3V 10/100 BASE TX INTEGRATED PHYCEIVER RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray
1894 功能描述:支架與墊片 HEX .187X.625 ALUM RoHS:否 制造商:Schurter 類型:Transipillar Spacers 長度:16 m 螺紋大小:M4 外徑:10 mm 材料:Nylon with Steel 電鍍:Zinc
1894# 制造商:Fluke Electronics 功能描述:BNC (F)/BANANA PLUG 制造商:Pomona Electronics 功能描述:
1894 制造商:Pomona Electronics 功能描述:ADAPTER BNC FEMALE-BANANA PLUG 制造商:Pomona Electronics 功能描述:ADAPTER, BNC FEMALE-BANANA PLUG