參數(shù)資料
型號(hào)： 21145
廠商： Intel Corp.
英文描述： Phoneline/Ethernet LAN Controller(電話線/以太網(wǎng)LAN控制器)
中文描述： 電話線/以太網(wǎng)控制器（電話線/以太網(wǎng)局域網(wǎng)控制器）
文件頁(yè)數(shù)： 12/50頁(yè)
文件大?。?/td> 624K
代理商： 21145
21145
6
Preliminary
Datasheet
P = Power
Pins labeled rsv are reserved for future use and must be left unconnected.
The following signals have an internal pull-up:
sr_do
mii/sym_tclk
Signal sr_cs has an internal pull-down.
Table 1
provides a functional description of each of the 21145 signals. These signals are listed
alphabetically.
Table 1. Functional Description of 21145 Signals (Sheet 1 of 8)
Signal
Type
Pin
Number,
176-pin
Pin
Number,
144-pin
Description
ad<31:0>
I/O
31, 32, 33,
35, 36, 37,
39, 40, 47,
48, 49, 51,
52, 53, 56,
57, 76, 77,
80, 81, 82,
84, 85, 86,
92, 93, 94,
96, 97, 98,
100, 101
23, 24, 25,
27, 28, 29,
31, 32, 39,
40, 41, 43,
44, 45, 47,
48, 61, 62,
64, 65, 66,
68, 69, 70,
76, 77, 78,
80, 81, 82,
84, 85
32-bit PCI address and data lines. Address and data bits
are multiplexed on the same pins. During the first clock
cycle of a transaction, the address bits contain a physical
address (32 bits). During subsequent clock cycles, these
same lines contain 32 bits of data. A 21145 bus
transaction consists of an address phase followed by one
or more data phases. The 21145 supports both read and
write bursts (in master operation mode only). Little and
big endian byte ordering can be used.
br_a<0>/cb_pads_l/
mdm_wr (on 176 pins)
br_a<0>/cb_pads_l
(on 144 pins)
I/O
105
87
For the 176-pin 21145 only
:
During operation, when accessing the modem chipset
(mdm_chip_sel is asserted), this pin is used as the
modem write line and is active low.
When the modem is not accessed (mdm_chip_sel is
deasserted), this pin is used as the expansion ROM
address line bit 0. In a 256KB configuration, this pin also
carries in two consecutive address cycles, expansion
ROM address bits 16 and 17.
For both the 144-pin and 176-pin 21145
:
During reset, this pin also determines the type of signals
to use for the PCI/CardBus output pins, either PCI or
CardBus. By default, this pin selects PCI signaling. To
select CardBus signaling, this pin must be connected to a
pull-down resistor.
br_a<1>/mdm_rd
O
106
NA
For the 176-pin 21145 only
:
During operation, when accessing the modem chipset
(mdm_chip_sel is asserted), this pin is used as the
modem read line and is active low.
When the modem is not accessed (mdm_chip_sel is
deasserted), this pin is used as the expansion ROM
address line bit 1. This pin also latches the expansion
ROM address and control lines by the two external
latches.
相關(guān)PDF資料
PDF描述
21150AA PCI Bus Interface/Controller
21150AB PCI Bus Interface/Controller
21152AA PCI Bus Interface/Controller
21152AB PCI Bus Interface/Controller
21153AA PCI Bus Interface/Controller
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