參數(shù)資料
型號(hào)： 21145
廠商： Intel Corp.
英文描述： Phoneline/Ethernet LAN Controller(電話線/以太網(wǎng)LAN控制器)
中文描述： 電話線/以太網(wǎng)控制器（電話線/以太網(wǎng)局域網(wǎng)控制器）
文件頁(yè)數(shù)： 37/50頁(yè)
文件大?。?/td> 624K
代理商： 21145
21145
Preliminary
Datasheet
31
3.10.3
SYM 10/100 Mb/s Timing—Signal Detect
Figure 12
shows the SYM port signal detect timing characteristics, and
Table 27
lists the SYM port
signal detect timing limits.
T
ts
3
mii/sym_rxd setup (both rise and fall
transactions) to mii/sym_rclk rise time or
mii_dv setup (both rise and fall transactions)
to mii_rclk rise time
8
—
—
ns
T
th
mii/sym_rxd hold (both rise and fall
transactions) after mii/sym_rclk rise time or
mii_dv hold (both rise and fall transactions)
after mii_rclk rise time
10
—
—
ns
NOTES:
1. ±50 parts per million.
2. t=1 for 100 Mb/s operation; t=10 for 10 Mb/s operation.
3. The receive data (mii/sym_rxd) and data valid (mii_dv) input pins are latched internally on the rising
edge of mii/sym_rclk.
Table 26.
MII/SYM Port Timing Limits—Receive (Sheet 2 of 2)
Symbol
Definition
Minimum
Typical
Maximum
Unit
Figure 12. SYM Port Timing Diagram—Signal Detect
Table 27. SYM Port Timing Limits—Signal Detect
Symbol
Definition
Minimum
Maximum
Units
T
ts
1
sd setup (both rise and fall transactions) to
sym_rclk fall time
10
—
ns
T
th
1
sd hold (both rise and fall transactions) after
sym_rclk fall time
12
—
ns
NOTE:
1. Input signal detect (sd) is latched internally on the falling edge of sym_rclk.
A6452-01
sym_rclk
sd
T
ts
T
th
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相關(guān)代理商/技術(shù)參數(shù)
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211450-2 制造商:TE Connectivity 功能描述:CONN CIRC DIN F 5 POS SLDR RA TH 5TERM - Bulk
211455-000 制造商:TE Connectivity 功能描述:CBL 2CNDCTR 14AWG 4.83MM TN PLTD CPPR BLU/WH 600VAC - Cable Rools/Shrink Tubing
2-1145-89A-1 制造商: 功能描述: 制造商:undefined 功能描述:
2-1145-A89-1 制造商: 功能描述: 制造商:undefined 功能描述:
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