參數(shù)資料
型號： 21145
廠商： Intel Corp.
英文描述： Phoneline/Ethernet LAN Controller(電話線/以太網(wǎng)LAN控制器)
中文描述： 電話線/以太網(wǎng)控制器（電話線/以太網(wǎng)局域網(wǎng)控制器）
文件頁數(shù)： 18/50頁
文件大?。?/td> 624K
代理商： 21145
21145
12
Preliminary
Datasheet
sr_di
O
137
113
Serial ROM data-in signal. This pin serially shifts the write
data from the 21145 to the serial ROM device.
sr_do
I
136
112
Serial ROM data-out signal. This pin serially shifts the
read data from the serial ROM device to the 21145.
stop_l
I/O
71
56
Stop indicator indicates that the current target is
requesting the bus master to stop the current transaction.
The 21145 responds to the assertion of stop_l when it is
the bus master, either to disconnect, retry, or abort.
tp_rd–
I
10
10
Twisted-pair negative differential receive data from the
twisted-pair lines.
tp_rd+
I
9
9
Twisted-pair positive differential receive data from the
twisted-pair lines.
tp_td–
tp_td– –
O
O
5
4
5
4
Twisted-pair negative differential transmit data. The
positive and negative differential transmit data outputs
are combined resistively outside the 21145 with
equalization to compensate for intersymbol interference
on the twisted-pair medium.
tp_td+
tp_td+ +
O
O
6
7
6
7
Twisted-pair positive differential transmit data. The
positive and negative differential transmit data outputs
are combined resistively outside the 21145 with
equalization to compensate for intersymbol interference
on the twisted-pair medium.
trdy_l
I/O
61
52
Target ready indicates the target agent’s ability to
complete the current data phase of the transaction.
A data phase is completed on any clock when both trdy_l
and irdy_l are asserted. Wait cycles are inserted until
both irdy_l and trdy_l are asserted together.
When the 21145 is the bus master, target ready is
asserted by the bus slave on the read operation, which
indicates that valid data is present on the ad lines. During
a write cycle, it indicates that the target is prepared to
accept data.
vcap_h
I
134
110
Capacitor input for analog phase-locked loop logic.
vdd
P
1, 2, 8, 25,
26, 34, 44,
45, 54, 67,
68, 83, 88,
89, 95, 113,
130, 131,
157, 168,
173
1, 2, 8, 18,
26, 36, 37,
46, 54, 67,
72, 73, 79,
95, 107, 125,
136, 141
3.3-V supply input. These pins should be connected to
the auxiliary power, if such power exists. Otherwise, these
pins should be connected to the main power.
vddac
P
133, 135
109,111
Supplies +3.3-V input for analog phase-locked loop logic.
These pins should each be decoupled with a separate 0.1
μf capacitor to ground. The capacitors should be located
as close to the package pins as possible.
vdd_clamp
P
28
20
Supplies +5-V or +3.3-V reference for clamp logic. This
pin is also used to determine the lack of main power when
the auxiliary power is on. It should be connected to the
main power.
This pin determines whether 5 V or 3.3 V signalling is
used on the PCI bus.
Table 1. Functional Description of 21145 Signals (Sheet 7 of 8)
Signal
Type
Pin
Number,
176-pin
Pin
Number,
144-pin
Description
相關(guān)PDF資料
PDF描述
21150AA PCI Bus Interface/Controller
21150AB PCI Bus Interface/Controller
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21152AB PCI Bus Interface/Controller
21153AA PCI Bus Interface/Controller
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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211450-2 制造商:TE Connectivity 功能描述:CONN CIRC DIN F 5 POS SLDR RA TH 5TERM - Bulk
211455-000 制造商:TE Connectivity 功能描述:CBL 2CNDCTR 14AWG 4.83MM TN PLTD CPPR BLU/WH 600VAC - Cable Rools/Shrink Tubing
2-1145-89A-1 制造商: 功能描述: 制造商:undefined 功能描述:
2-1145-A89-1 制造商: 功能描述: 制造商:undefined 功能描述:
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