參數(shù)資料
型號: 21145
廠商: Intel Corp.
英文描述: Phoneline/Ethernet LAN Controller(電話線/以太網(wǎng)LAN控制器)
中文描述: 電話線/以太網(wǎng)控制器(電話線/以太網(wǎng)局域網(wǎng)控制器)
文件頁數(shù): 36/50頁
文件大?。?/td> 624K
代理商: 21145
21145
30
Preliminary
Datasheet
3.10.2
MII/SYM 10/100 Mb/s Timing—Receive
Figure 11
shows the MII/SYM port receive timing characteristics, and
Table 26
lists the MII/SYM
port receive timing limits.
Table 25.
MII/SYM Port Timing Limits—Transmit
Symbol
Definition
Minimum
Typical
Maximum
Unit
T
cc
1
mii/sym_tclk cycle
40t
2
ns
T
ch
mii/sym_tclk high time
14t
2
26t
2
ns
T
cl
mii/sym_tclk low time
14t
2
26t
2
ns
T
cr
mii/sym_tclk rise time
8
ns
T
cf
mii/sym_tclk fall time
8
ns
T
val
mii_tclk rise to mii_txen valid time or
mii/sym_tclk rise
to mii/sym_txd valid time
0
20
ns
NOTES:
1. ±50 parts per million.
2. t=1 for 100 Mb/s operation; t=10 for 10 Mb/s operation.
Figure 11.
MII/SYM Port Timing Diagram—Receive
Table 26. MII/SYM Port Timing Limits—Receive (Sheet 1 of 2)
Symbol
Definition
Minimum
Typical
Maximum
Unit
T
cc
1
mii/sym_rclk cycle time
40t
2
ns
T
c
mii/sym_rclk high time
14t
2
26t
2
ns
T
cl
mii/sym_rclk low time
14t
2
26t
2
ns
T
cr
mii/sym_rclk rise time
8
ns
T
cf
mii/sym_rclk fall time
8
ns
A6451-01
mii/sym_rclk
mii/sym_rxd<3:0>
mii_dv
T
cc
T
ch
T
ts
T
th
T
cl
T
cf
T
cr
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