參數(shù)資料
型號(hào)： 21145
廠商： Intel Corp.
英文描述： Phoneline/Ethernet LAN Controller(電話線/以太網(wǎng)LAN控制器)
中文描述： 電話線/以太網(wǎng)控制器（電話線/以太網(wǎng)局域網(wǎng)控制器）
文件頁(yè)數(shù)： 17/50頁(yè)
文件大?。?/td> 624K
代理商： 21145
21145
Preliminary
Datasheet
11
mii/sym_txd<3:0>
O
148, 149,
150, 151
119, 120,
121, 122
Four parallel transmit data lines. This data is
synchronized to the assertion of the mii_tclk signal and is
latched by the external PHY on the rising edge of the
mii_tclk signal.
mii_txen/sym_txd<4>
O
152
123
In MII mode, this pin functions as transmit enable. It
indicates that a transmission is active on the MII port to
an external PHY device.
In SYM mode, this pin functions as transmit data. This
line along with the four data transmit lines (sym_txd<3:0>)
provides five parallel data lines in symbol form. The data
is synchronized to the rising edge of the sym_tclk signal.
par
I/O
74
59
Parity is calculated by the 21145 as an even parity bit for
the 32-bit ad and 4-bit c_be_l lines.
During address and data phases, parity is calculated on
all the ad and c_be_l lines whether or not any of these
lines carry meaningful information.
pci_clk
I
27
19
The clock provides the timing for the 21145 related PCI
bus transactions. All the bus signals are sampled on the
rising edge of pci_clk. The supported clock frequency
range is 20 MHz to 33 MHz.
perr_l
I/O
72
57
Parity error asserts when a data parity error is detected.
When the 21145 is the bus master and a parity error is
detected, the 21145 asserts both CSR5 bit 13 (fatal bus
error) and CFCS bit 24 (data parity report). Next, it
completes the current data burst transaction, then stops
operation. After the host clears the system error via
CSR5<13>, the 21145 continues its operation.
The 21145 asserts perr_l when a data parity error is
detected in either a master-read or a slave-write
operation.
req_l
O
30
22
Bus request is asserted by the 21145 to indicate to the
bus arbiter that it wants to use the bus.
rst_l
I
22
16
Resets the 21145 to its initial state. This signal must be
asserted for at least 10 active PCI clock cycles. When in
the reset state, all PCI output pins are put into tristate and
all PCI O/D signals are floated.
rsv
—
15, 16, 17,
63, 145, 170,
171, 172
88, 89, 90,
92, 93, 96,
97, 98, 99,
138, 139,
140
Reserved. These pins should remain unconnected.
rsv_vdd
I
55
NA
Must be connected to Vdd for proper operation.
serr_l
O/D
73
58
If an address parity error is detected and CFCS bit 8
(serr_l enable) is enabled, 21145 asserts both serr_l
(system error) and CFCS bit 30 (signal system error).
When an address parity error is detected, system error
asserts two clocks after the failing address.
sr_ck
O
138
114
Serial ROM clock signal. This pin provides a serial clock
output for the serial ROM.
sr_cs
O
139
115
Serial ROM chip-select signal. This pin provides a chip
select for the serial ROM.
Table 1. Functional Description of 21145 Signals (Sheet 6 of 8)
Signal
Type
Pin
Number,
176-pin
Pin
Number,
144-pin
Description
相關(guān)PDF資料
PDF描述
21150AA PCI Bus Interface/Controller
21150AB PCI Bus Interface/Controller
21152AA PCI Bus Interface/Controller
21152AB PCI Bus Interface/Controller
21153AA PCI Bus Interface/Controller
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211450-2 制造商:TE Connectivity 功能描述:CONN CIRC DIN F 5 POS SLDR RA TH 5TERM - Bulk
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2-1145-89A-1 制造商: 功能描述: 制造商:undefined 功能描述:
2-1145-A89-1 制造商: 功能描述: 制造商:undefined 功能描述:
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