參數(shù)資料
型號(hào): 21145
廠商: Intel Corp.
英文描述: Phoneline/Ethernet LAN Controller(電話線/以太網(wǎng)LAN控制器)
中文描述: 電話線/以太網(wǎng)控制器(電話線/以太網(wǎng)局域網(wǎng)控制器)
文件頁(yè)數(shù): 38/50頁(yè)
文件大?。?/td> 624K
代理商: 21145
21145
32
Preliminary
Datasheet
3.10.4
MII 10/100 Mb/s Timing—Receive Error
Figure 13
shows the MII port receive error timing characteristics, and
Table 28
lists the MII port
receive error timing limits.
3.10.5
MII 10/100 Mb/s Timing—Carrier Sense and Collision
Figure 14
shows the MII port carrier sense and collision timing characteristics, and
Table 29
lists
the MII port carrier sense and collision timing limits.
Figure 13.
MII Port Timing Diagram—Receive Error
Table 28. MII Port Timing Limits—Receive Error
Symbol
Definition
Minimum
Maximum
Unit
Tts
1
mii_rx_err setup (both rise and fall
transactions) to mii_rclk rise time
10
ns
Tth
1
mii_rx_err hold (both rise and fall
transactions) after mii_rclk rise time
10
ns
NOTE:
1. Input signal detect (mii_rx_err) is latched internally on the falling edge of mii_rclk.
A6453-01
mii_rclk
mii_rx_err
T
ts
T
th
Figure 14.
MII Port Timing Diagram—Carrier Sense and Collision
Table 29. MII Port Timing Limits—Carrier Sense and Collision
Symbol
Definition
Minimum
Maximum
Unit
Tclh
mii_crs, mii_clsn high time
80
ns
A6455-01
mii_clsn
mil_crs
T
clh
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