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參數(shù)資料
| 型號： | 21145 |
| 廠商： | Intel Corp. |
| 英文描述： | Phoneline/Ethernet LAN Controller(電話線/以太網(wǎng)LAN控制器) |
| 中文描述： | 電話線/以太網(wǎng)控制器（電話線/以太網(wǎng)局域網(wǎng)控制器） |
| 文件頁數(shù)： | 8/50頁 |
| 文件大?。?/td> | 624K |
| 代理商： | 21145 |
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21145
2
Preliminary
Datasheet
The MII/SYM port supports two operational modes:
MII mode—A full implementation of the MII standard
SYM mode—Symbol interface to an external 100 Mb/s front-end decoder (ENDEC). In this
mode the 21145 uses an onchip physical coding sublayer (PCS) and a scrambler/descrambler
circuit to enable a low-cost 100BASE-T implementation.
The 21145 is capable of functioning in a full-duplex environment for the MII/SYM and 10BASE-T
ports.
1.3
21145 Block Diagram
The following list describes the 21145 hardware components, and
Figure 1
shows a block diagram
of the 21145:
PCI/CardBus interface—Includes all interface functions to the PCI and CardBus bus. Handles
all interconnect control signals; and executes DMA and I/O transactions.
Boot ROM/Modem port—Provides an interface to perform read and write operations to ISA
compliant modem chipsets and to the boot ROM; supports accesses to bytes or longwords (32-
bit) to the boot ROM. Provides the ability to connect an external 8-bit register to the boot
ROM port.
Serial ROM port—Provides a direct interface to a MicroWire ROM for storage of the Ethernet
address and system parameters.
General-purpose register—Enables software use for input or output functions and LEDs.
DMA—Contains independent receive and transmit controllers; handles data transfers between
CPU memory and onchip memory.
FIFOs—Contains independent FIFOs for receive and transmit. Supports automatic packet
deletion on receive (runt packets or after a collision) and packet retransmission after a collision
on transmit.
RxM—Handles all CSMA/CD
1
receive operations, and transfers the network data from the
ENDEC to the receive FIFO.
TxM—Handles all CSMA/CD MAC
2
transmit operations, and transfers data from transmit
FIFO to the ENDEC for transmission.
SIA interface—Performs 10 Mb/s physical layer network operations; implements the
HomePNA and 10BASE-T functions, including the Manchester encoder and decoder
functions.
NWAY—Implements the IEEE 802.3 Auto-Negotiation algorithm.
Physical coding sublayer—Implements the encoding and decoding sublayer of the 100BASE-
TX (CAT5) specification, including the squelch feature.
HomePNA PHY—Implements the HomePNA telephone network interface.
Scrambler/descrambler—Implements the twisted-pair physical layer medium dependent
(TP-PMD) scrambler/descrambler scheme for 100BASE-TX.
1. Carrier-sense multiple access with collision detection.
2. Media access control.
相關PDF資料 |
PDF描述 |
|---|---|
| 21150AA | PCI Bus Interface/Controller |
| 21150AB | PCI Bus Interface/Controller |
| 21152AA | PCI Bus Interface/Controller |
| 21152AB | PCI Bus Interface/Controller |
| 21153AA | PCI Bus Interface/Controller |
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