參數(shù)資料
型號(hào)： 21145
廠商： Intel Corp.
英文描述： Phoneline/Ethernet LAN Controller(電話線/以太網(wǎng)LAN控制器)
中文描述： 電話線/以太網(wǎng)控制器（電話線/以太網(wǎng)局域網(wǎng)控制器）
文件頁(yè)數(shù)： 13/50頁(yè)
文件大?。?/td> 624K
代理商： 21145
21145
Preliminary
Datasheet
7
br_ad<7:0>/
<mdm<7:0>
I/O
107, 108,
110, 111,
114, 115,
117, 118
NA
For the 176-pin 21145 only
:
During operation, when accessing the modem chipset
(mdm_chip_sel is asserted), these pins are used as the
modem data lines bits 7 through 0. When the modem is
not accessed (mdm_chip_sel is deasserted), these pins
are used as the expansion ROM address and data lines.
br_ce_l
O
104
NA
Expansion ROM or external register chip enable.
c_be_l<3:0>
I/O
41, 58, 75,
91
33, 49, 60,
75
Bits 0 through 3 of the bus command and byte enable
lines. Bus command and byte enable are multiplexed on
the same PCI pins.
During the address phase of the transaction, these 4 bits
provide the bus command.
During the data phase, these 4 bits provide the byte
enable. The byte enable determines which byte lines
carry valid data. For example, bit 0 applies to byte 0, and
bit 3 applies to byte 3.
clkrun_l
I/O
O/D
102
86
PCI/CardBus clock run indication. The host system
asserts this signal to indicate normal operation of the
clock. The host system deasserts clkrun_l when the clock
is going to be stopped or slowed down to a
nonoperational frequency.
If the clock is needed by the 21145, the 21145 asserts
clkrun_l, requesting normal clock operation to be
maintained or restored. Otherwise, the 21145 allows the
system to stop the clock.
devsel_l
I/O
69
55
Device select is asserted by the target of the current bus
access. When the 21145 is the initiator of the current bus
access, it expects the target to assert devsel_l within 5
bus cycles, confirming the access. If the target does not
assert devsel_l within the required bus cycles, the 21145
aborts the cycle. To meet the timing requirements, the
21145 asserts this signal in a medium speed (within 2 bus
cycles).
frame_l
I/O
59
50
The frame_l signal is driven by the bus master to indicate
the beginning and duration of an access. The frame_l
signal asserts to indicate the beginning of a bus
transaction. While frame_l is asserted, data transfers
continue. The frame_l signal deasserts to indicate that the
next data phase is the final data phase transaction.
gep<0>
I/O
123
100
This pin can be configured by software to be a general-
purpose pin that performs either input or output functions.
This general-purpose pin can provide an interrupt when
functioning as an input.
gep<1>/activ
I/O
124
101
This pin can be configured by software to be:
A general-purpose pin that performs either input or
output functions. This general-purpose pin can
provide an interrupt when functioning as an input.
A status pin that provides an LED that indicates
either receive or transmit activity.
Table 1. Functional Description of 21145 Signals (Sheet 2 of 8)
Signal
Type
Pin
Number,
176-pin
Pin
Number,
144-pin
Description
相關(guān)PDF資料
PDF描述
21150AA PCI Bus Interface/Controller
21150AB PCI Bus Interface/Controller
21152AA PCI Bus Interface/Controller
21152AB PCI Bus Interface/Controller
21153AA PCI Bus Interface/Controller
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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211450-2 制造商:TE Connectivity 功能描述:CONN CIRC DIN F 5 POS SLDR RA TH 5TERM - Bulk
211455-000 制造商:TE Connectivity 功能描述:CBL 2CNDCTR 14AWG 4.83MM TN PLTD CPPR BLU/WH 600VAC - Cable Rools/Shrink Tubing
2-1145-89A-1 制造商: 功能描述: 制造商:undefined 功能描述:
2-1145-A89-1 制造商: 功能描述: 制造商:undefined 功能描述:
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