Clock Generator Specification for AMD64 Processors
24707 Rev. 3.08 September 2003
other spread amounts less than 0.5% down spread and less than 50 kHz
f/
t modulation are left
to the clock generator vendor to include as differentiating features.
1.3.1
Reserved Test Mode Operating States
This specification defines two test modes and reserves one other for the purpose of providing
required system debug and system test operating modes. The reserved manufacturer test mode is
provided for each clock vendor to implement an operating mode specific to their own production
test flow needs and is not required for system operation.
1.4
Differential Push-Pull Processor Clock Outputs
This clock generator is specified to provide push-pull driver type differential outputs for the
processor clocks (2-pair) instead of the common open drain style used for AMD Athlon processor-
based platforms. This provides a more testable product and results in less variation in edge rate
and differential skew as seen by the processor. The processor clock termination scheme has been
derived such that 15–55 ohm, 3.3-V output drivers can be used for the processor clocks.
1.5
Selectable 33-MHz or 66-MHz Clock Outputs
This clock generator specification defines a number of clock outputs that are selectable between
33 MHz and 66 MHz. This selection provides flexibility across platforms that may implement a
combination of 33-MHz PCI resources, 66-MHz PCI resources, and HyperTransport technology
resources.
Note
: HyperTransport technology is the HyperTransport Technology Consortium’s next
generation interconnect technology that is designed for use with all AMD64 platforms.
1.6
PCISTOP33_L Control Signal
This clock generator specification defines one asynchronous PCISTOP33_L signal that provides
control for 33-MHz output clocks. Both the PCI33 and PCI33_HT66 clocks, while operating at
33MHz, must stop in response to PCISTOP33_L assertions. While operating at 66 MHz, the
PCI33_HT66 outputs are not affected by PCISTOP33_L assertions.
The 33-MHz PCI clock outputs, once stopped, should be in the Low state and started with a full
high-pulse width specified. The 33-MHz PCI clock outputs on latency cycles are only one rising
PCI clock turned off. Latency is one PCI clock. Section 1.6.1 and Section 1.6.2 on page 7, along
with Figure 1 on page 7 gives a description and timing diagram respectively, of the required
timing sequence:
1.6.1
Starting the 33-MHz PCI Clocks
The 33MHz PCI clocks must be started using the following sequence of events:
6
Description
Chapter 1