參數(shù)資料
型號(hào)： 24707_PUB
英文描述： Programmable Resolution 1-Wire Digital Thermometer
中文描述： 時(shí)鐘發(fā)生器規(guī)格的AMD Athlon？ 64和AMD Opteron？處理器
文件頁(yè)數(shù)： 50/51頁(yè)
文件大?。?/td> 1783K
代理商： 24707_PUB
Clock Generator Specification for AMD64 Processors
24707 Rev. 3.08 September 2003
Table 23. Byte6: Reserved for Byte Count
Bit
Default
Description
7
6
5
4
3
2
1
0
Reserved for device specific read byte count=MSB
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
This register contains the number of bytes that the clock generator returns when issued a block
read command. It is defined and reserved such that additional bytes can be added as the clock
generator vendor sees fit. This register should contain the total number of bytes returned by a
block read command including vendor specific bytes above 6. Should a clock vendor wish to
provide test/debug mode registers above byte 6, this value can remain defaulted to 6 and later
updated through an SMBus write to allow access to these test/debug registers.
ATPG Function
—This feature is only used during processor burn-in and is an optional feature
for the clock vendor to implement.
Two SMBus register bits are required to implement this feature:
ATPG Mode Bit
—Enables/Disables ATPG mode
ATPG Pulse Bit—Triggers a single CPUclk pulse when set
Assuming that the clock synthesizer is operating either in Normal mode or PLL bypass mode, the
following sequence can be followed to generate an ATPG pulse.
Set the Write Enable Bit (Byte/Bit 0) to program the Clock Synthesizer registers using the SM
Bus.
Use the ATPG Mode Bit in the clock synthesizer configuration space to enable/disable the
ATPG mode. When this bit is set, the ATPG mode is enabled and the differential processor
clock outputs are pulled in differential low state (CPUT = 0 and CPUC = 1). The ATPG mode
also requires the USBclk (48MHz) to run as usual. All other clocks (PCI, Ref, PCI33_66,
SuperIO are not used by the ATPG mode therefore can either be left running or shut off.
Use the ATPG pulse bit in the clock synthesizer program space to generate the ATPG pulse.
When the ATPG pulse bit is set, a differential ATPG pulse is generated on the differential
processor clock pins. The pulse width of the ATPG pulse is one processor clock period. The
processor clock period in the ATPG mode is same as the one in Normal mode or PLL bypass
mode.
46
SMBus Interface
Chapter 8
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
24-7080-0018 制造商:Kester 功能描述:SN95SB05 #66/44 .025 1 LB SPL Solder Wire
24-7080-0027 制造商:Kester 功能描述:SN95SB05 #66/44 .031 1 LB SPL Solder Wire
24-7080-0060 功能描述:SOLDER FLUX-CORED/44 .062" 1LB S 制造商:kester solder 系列:44 零件狀態(tài):在售 類型:焊線 成分:Sn95Sb5（95/5） 熔點(diǎn):450 ~ 464°F（232 ~ 240°C） 直徑:0.062"（1.57mm） 焊劑類型:活性松香（RA） 線規(guī):16 AWG，18 SWG 工藝:無(wú)鉛 形式:線軸, 1 磅 (454 g) 保質(zhì)期:36 個(gè)月（制造日期） 發(fā)貨信息:- 標(biāo)準(zhǔn)包裝:25
24-7080-0061 制造商:Kester 功能描述:SN95SB05 #66/44 .062 1 LB SPL Solder Wire
24-7080-0634 功能描述:SOLDER FLUX-CORED/OR421 .032 1LB 制造商:kester solder 系列:OR421 零件狀態(tài):在售 類型:焊線 成分:Sn95Sb5（95/5） 熔點(diǎn):450 ~ 464°F（232 ~ 240°C） 直徑:0.032"（0.81mm） 焊劑類型:水溶性 線規(guī):21 AWG，22 SWG 工藝:無(wú)鉛 形式:線軸, 1 磅 (454 g) 保質(zhì)期:無(wú)保質(zhì)期 發(fā)貨信息:- 標(biāo)準(zhǔn)包裝:25
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