參數(shù)資料
型號: 24707_PUB
英文描述: Programmable Resolution 1-Wire Digital Thermometer
中文描述: 時(shí)鐘發(fā)生器規(guī)格的AMD Athlon? 64和AMD Opteron?處理器
文件頁數(shù): 47/51頁
文件大?。?/td> 1783K
代理商: 24707_PUB
24707 Rev. 3.08 September 2003
Clock Generator Specification for AMD64 Processors
Table 17. Byte0: Frequency and Spread Spectrum Control Register (Continued)
Bit
Default
Description
3
2
1
0
Inactive=0
Inactive=0
Inactive=0
Inactive=0
FS2 (corresponds to Table 2, on page 11)
FS1 (corresponds to Table 2, on page 11)
FS0 (corresponds to Table 2, on page 11)
Write Enable. A 1 written to this bit after power up will enable modification of all
configuration registers and subsequent zeros written to this bit will disable
modification of all configurations except this single bit. Note that when a 1 has been
written to Byte0 bit 7 all modification is permanently disabled until the device power
cycles. Note also that block write transactions to the interface will complete,
however unless the interface has been previously unlocked, the writes will have no
effect. The effect of writing this bit does not take effect until the subsequent block
write command.
Note
: FS[2:0] are the only required FS inputs and represent the only required operating states of the
device. FS[4:3] are defined and reserved so that implementations that provide a larger FS table
with additional operating states are enabled. None of these additional operating states are
required by the baseline feature set of the platforms that we envision, however, may serve customer
requirements or desires. When Byte 0 is read, the current state of the register should be returned,
not FS[2:0] or SPREAD pin states. These pin states are provided in Byte4.
The process of changing the FS bits thru software is as follows:
1. Upon powerup, Byte0, bits[5:1], and FS[4:0] are set to the default hardware settings.
2. A 1 is written to Byte0, bit0 to enable software control.
3. Every time Byte0 is written, the FIDs are affected.
4. If a 0 is written to Byte0, bit0 the software control is disabled. Disabling software control does
not cause the contents of Byte0 to default back to hardware setting for FS[4:0].
Table 18 outlines the register settings for the PCI clock control.
Table 18. Byte1: PCI Clock Control Register (1=Enabled, 0=Disabled)
Bit
Default
Description
7
6
5
4
3
2
1
0
Note
: If a clock is set to free-running in Byte3and Byte 4, it can still be shut off using Byte1 or Byte2.
Active=1
Active=1
Active=1
Active=1
Active=1
Active=1
Active=1
Active=1
PCI33_HT66(1) enable (1=Enabled, 0=Disabled)
PCI33_HT66(0) enable (1=Enabled, 0=Disabled)
PCI33(5) enable (1=Enabled, 0=Disabled)
PCI33(4) enable (1=Enabled, 0=Disabled)
PCI33(3) enable (1=Enabled, 0=Disabled)
PCI33(2) enable (1=Enabled, 0=Disabled)
PCI33(1) enable (1=Enabled, 0=Disabled)
PCI33(0) enable (1=Enabled, 0=Disabled)
Chapter 8
SMBus Interface
43
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