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| 型號(hào)： | 24707_PUB |
| 英文描述： | Programmable Resolution 1-Wire Digital Thermometer |
| 中文描述： | 時(shí)鐘發(fā)生器規(guī)格的AMD Athlon？ 64和AMD Opteron？處理器 |
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24707 Rev. 3.08 September 2003
Clock Generator Specification for AMD64 Processors
Table 3. Pin Locations and Descriptions (Continued)
Name
Pin
No. of
Pins
Type
Pin Description
PCISTOP33_L
24
1
I
Control for PCI33[0:5] and PCI33_HT66[0:2]
outputs operating at 33-MHz:
Active-Low control
input to halt all 33-MHz PCI clocks except the free-
running clock. This input must have a weak internal
pullup resistor (100 K). Once this input has been
asserted, the PCI33 outputs and PCI33_HT66 outputs
operating at 33MHz must stop in the Low state
according to the timing diagram outlined in Section
1.6.2 on page 7 and must not violate the output duty
cycle requirements until stopped (no glitches or runt
cycles).
Low = stop, High = running.
Pin reserved for vendor specific features.
Data pin for I
2
C circuitry (SM Bus Rev1.0). This
input should have weak internal pullup resistor (100
K). In this case, no external pullup resistors would be
required. SDATA is a 5.0-V tolerant I/O.
Note Option:
If CLK vendor only supports 3.3-V
tolerant I/O, they must provide an application
note in their spec on how to handle a 5V SMBus
(i.e., clamp circuit on the motherboard).
Clock pin for I
2
C circuitry (SM Bus Rev1.0). This
input must have weak internal pullup resistors (100K).
In this case, no external pullup resistors would be
required. SCLK must be a 3.3-V signal-tolerant I/O
but not 5.0-V tolerant..
Power Connection:
Connected to 3.3 V power
supply. Used to supply digital portions of the chip.
NC
SDATA
12
26
1
1
I/O
SCLK
25
1
I
VDD
2
9
16
19
29
35
38
46
8
P
Chapter 5
Pin Locations and Descriptions
21
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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