參數(shù)資料
型號(hào): 24C01SC
廠商: Microchip Technology Inc.
英文描述: 1K 5.0V IIC serial EEPROMs(2.5V~5.5V,1K位,1M次擦寫(xiě)周期,ISO7816標(biāo)準(zhǔn))
中文描述: 一千5.0V國(guó)際進(jìn)口電壓(2.5V?5.5V的,每1000位,100萬(wàn)次擦寫(xiě)周期,符合ISO7816標(biāo)準(zhǔn)串行EEPROM)
文件頁(yè)數(shù): 105/170頁(yè)
文件大?。?/td> 4191K
代理商: 24C01SC
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)當(dāng)前第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)
2003 Microchip Technology Inc.
Preliminary
DS40300C-page 103
PIC16F62X
TABLE 14-9:
SUMMARY OF INTERRUPT REGISTERS
14.7
Context Saving During Interrupts
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key
registers during an interrupt (e.g., W register and
STATUS register). This will have to be implemented in
software.
Example 14-2 stores and restores the STATUS and W
registers. The user register, W_TEMP, must be defined
in a common memory location (i.e., W_TEMP is
defined at 0x70 in Bank 0 and is therefore, accessible
at 0xF0, 0x17 and 0xIFD). The Example 14-2:
Stores the W register
Stores the STATUS register
Executes the ISR code
Restores the STATUS (and bank select bit
register)
Restores the W register
EXAMPLE 14-2:
SAVING THE STATUS
AND W REGISTERS IN
RAM
14.8
Watchdog Timer (WDT)
The Watchdog Timer is a free running on-chip RC
oscillator which does not require any external compo-
nents. This RC oscillator is separate from the ER
oscillator of the CLKIN pin. That means that the WDT
will run, even if the clock on the OSC1 and OSC2 pins
of the device has been stopped, for example, by
execution of a
SLEEP
instruction. During normal
operation, a WDT timeout generates a device RESET.
If the device is in SLEEP mode, a WDT timeout causes
the device to wake-up and continue with normal opera-
tion. The WDT can be permanently disabled by
programming the configuration bit WDTE as clear
(Section 14.1).
14.8.1
WDT PERIOD
The WDT has a nominal timeout period of 18 ms (with
no prescaler). The timeout periods vary with tempera-
ture, V
DD
and process variations from part to part (see
DC specs). If longer timeout periods are desired, a
postscaler with a division ratio of up to 1:128 can be
assigned to the WDT under software control by writing
to the OPTION register. Thus, timeout periods up to 2.3
seconds can be realized.
The
CLRWDT
and
SLEEP
instructions clear the WDT
and the postscaler, if assigned to the WDT, and prevent
it from timing out and generating a device RESET.
The TO bit in the STATUS register will be cleared upon
a Watchdog Timer timeout.
14.8.2
WDT PROGRAMMING
CONSIDERATIONS
It should also be taken in account that under worst case
conditions (V
DD
= Min., Temperature = Max., max.
WDT prescaler), it may take several seconds before a
WDT timeout occurs.
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR Reset
Value on all
other
RESETS
(1)
0Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 -000
0000 -000
0000 000u
0000 -000
0000 -000
0Ch
PIR1
EEIF
CMIF
RCIF
TXIF
CCP1IF
TMR2IF TMR1IF
8Ch
PIE1
EEIE
CMIE
RCIE
TXIE
CCP1IE TMR2IE TMR1IE
Note
1:
Other (non Power-up) Resets include MCLR Reset, Brown-out Detect Reset and Watchdog Timer Reset during normal
operation.
MOVWF
W_TEMP
;copy W to temp register,
could be in either bank
SWAPF
STATUS,W
;swap status to be saved
into W
BCF
STATUS,RP0
;change to bank 0 regardless
of current bank
MOVWF
STATUS_TEMP
;save status to bank 0
register
:
: (ISR)
:
SWAPF
STATUS_TEMP,W
;swap STATUS_TEMP register
into W, sets bank to origi-
nal
state
MOVWF
STATUS
;move W into STATUS register
SWAPF
W_TEMP,F
;swap W_TEMP
SWAPF
W_TEMP,W
;swap W_TEMP into W
相關(guān)PDF資料
PDF描述
24C02SC 2K 5.0V IIC serial EEPROMs(2.5V~5.5V,2K位,1M次擦寫(xiě)周期,ISO7816標(biāo)準(zhǔn))
24C02A 2K 5.0V CMOS serial EEPROMs(2K位,5.0V,IIC串行EEPROM)
24C02C 2K 5.0V IIC serial EEPROMs(2K位,1M次擦寫(xiě)周期,硬件寫(xiě)保護(hù),二線串行接口,EEPROM)
24C02C-EP 2K 5.0V I 2 C ⑩ Serial EEPROM
24C02C-ESN 2K 5.0V I 2 C ⑩ Serial EEPROM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
24C01SC/S 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SERIAL EEPROM|128X8|CMOS|DIE
24C01SC-/S 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:1K/2K 5.0V I2C Serial EEPROMs for Smart Cards
24C01SC/S08 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SERIAL EEPROM|128X8|CMOS|DIE
24C01SC-/S08 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:1K/2K 5.0V I2C Serial EEPROMs for Smart Cards
24C01SC/W 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SERIAL EEPROM|128X8|CMOS|WAFER