參數(shù)資料
型號(hào)： 24C01SC
廠商： Microchip Technology Inc.
英文描述： 1K 5.0V IIC serial EEPROMs(2.5V~5.5V,1K位,1M次擦寫周期,ISO7816標(biāo)準(zhǔn))
中文描述： 一千5.0V國際進(jìn)口電壓（2.5V?5.5V的，每1000位，100萬次擦寫周期，符合ISO7816標(biāo)準(zhǔn)串行EEPROM）
文件頁數(shù)： 79/170頁
文件大小： 4191K
代理商： 24C01SC
2003 Microchip Technology Inc.
Preliminary
DS40300C-page 77
PIC16F62X
12.2.2
ADEN USART ASYNCHRONOUS
RECEIVER
The receiver block diagram is shown in Figure 12-8.
The data is received on the RB1/RX/DT pin and drives
the data recovery block. The data recovery block is
actually a high speed shifter operating at x16 times the
baud rate, whereas the main receive serial shifter
operates at the bit rate or at F
OSC
.
Once Asynchronous mode is selected, reception is
enabled by setting bit CREN (RCSTA<4>).
The heart of the receiver is the Receive (serial) Shift
register (RSR). After sampling the STOP bit, the
received data in the RSR is transferred to the RCREG
register (if it is empty). If the transfer is complete, flag
bit RCIF (PIR1<5>) is set. The actual interrupt can be
enabled/disabled by setting/clearing enable bit RCIE
(PIE1<5>). Flag bit RCIF is a read only bit which is
cleared by the hardware. It is cleared when the RCREG
register has been read and is empty. The RCREG is a
double buffered register ( i.e., it is a two-deep FIFO).
It is possible for two bytes of data to be received and
transferred to the RCREG FIFO, and a third byte begin
shifting to the RSR register. On the detection of the
STOP bit of the third byte, if the RCREG register is still
full, then overrun error bit OERR (RCSTA<1>) will be
set. The word in the RSR will be lost. The RCREG
register can be read twice to retrieve the two bytes in
the FIFO. Overrun bit OERR has to be cleared in soft-
ware. This is done by resetting the receive logic (CREN
is cleared and then set). If bit OERR is set, transfers
from the RSR register to the RCREG register are inhib-
ited, so it is essential to clear error bit OERR if it is set.
Framing error bit FERR (RCSTA<2>) is set if a STOP
bit is detected as clear. Bit FERR and the 9th receive
bit are buffered the same way as the receive data.
Reading the RCREG will load bits RX9D and FERR
with new values, therefore it is essential for the user to
read the RCSTA register before reading the RCREG
register in order not to lose the old FERR and RX9D
information.
FIGURE 12-8:
USART RECEIVE BLOCK DIAGRAM
x64 Baud Rate CLK
SPBRG
Baud Rate Generator
RB1/RX/DT
Pin Buffer
and Control
SPEN
Data
Recovery
CREN
OERR
FERR
RSR register
MSb
LSb
RX9D
RCREG register
FIFO
Interrupt
RCIF
RCIE
Data Bus
8
3 64
or
3 16
Stop
Start
(8)
7
1
0
RX9
2 2 2
RX9
ADEN
RX9
ADEN
RSR<8>
Enable
Load of
Receive
Buffer
8
8
RCREG register
RX9D
相關(guān)PDF資料
PDF描述
24C02SC 2K 5.0V IIC serial EEPROMs(2.5V~5.5V,2K位,1M次擦寫周期,ISO7816標(biāo)準(zhǔn))
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參數(shù)描述
24C01SC/S 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SERIAL EEPROM|128X8|CMOS|DIE
24C01SC-/S 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:1K/2K 5.0V I2C Serial EEPROMs for Smart Cards
24C01SC/S08 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SERIAL EEPROM|128X8|CMOS|DIE
24C01SC-/S08 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:1K/2K 5.0V I2C Serial EEPROMs for Smart Cards
24C01SC/W 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SERIAL EEPROM|128X8|CMOS|WAFER
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