參數(shù)資料
型號(hào): 24C01SC
廠商: Microchip Technology Inc.
英文描述: 1K 5.0V IIC serial EEPROMs(2.5V~5.5V,1K位,1M次擦寫周期,ISO7816標(biāo)準(zhǔn))
中文描述: 一千5.0V國(guó)際進(jìn)口電壓(2.5V?5.5V的,每1000位,100萬(wàn)次擦寫周期,符合ISO7816標(biāo)準(zhǔn)串行EEPROM)
文件頁(yè)數(shù): 13/170頁(yè)
文件大?。?/td> 4191K
代理商: 24C01SC
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2003 Microchip Technology Inc.
Preliminary
DS40300C-page 11
PIC16F62X
2.1
Clocking Scheme/Instruction
Cycle
The clock input (OSC1/CLKIN/RA7 pin) is internally
divided by four to generate four non-overlapping
quadrature clocks namely Q1, Q2, Q3 and Q4.
Internally, the program counter (PC) is incremented
every Q1, the instruction is fetched from the program
memory and latched into the instruction register in Q4.
The instruction is decoded and executed during the
following Q1 through Q4. The clocks and instruction
execution flow is shown in Figure 2-2.
2.2
Instruction Flow/Pipelining
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change, (e.g.,
GOTO
)
then two cycles are required to complete the instruction
(Example 2-1).
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the “Instruction Register (IR)” in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3, and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 2-2:
CLOCK/INSTRUCTION CYCLE
EXAMPLE 2-1:
INSTRUCTION PIPELINE FLOW
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
Q1
Q2
Q3
Q4
PC
CLKOUT
PC
PC+1
PC+2
Fetch INST (PC)
Execute INST (PC-1)
Fetch INST (PC+1)
Execute INST (PC)
Fetch INST (PC+2)
Execute INST (PC+1)
Internal
phase
clock
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction
is “flushed” from the pipeline while the new instruction is being fetched and then executed.
1. MOVLW 55h
Fetch 1
Execute 1
2. MOVWF PORTB
Fetch 2
Execute 2
3. CALL SUB_1
Fetch 3
Execute 3
4. BSF PORTA, 3
Fetch 4
Flush
Fetch SUB_1 Execute SUB_1
相關(guān)PDF資料
PDF描述
24C02SC 2K 5.0V IIC serial EEPROMs(2.5V~5.5V,2K位,1M次擦寫周期,ISO7816標(biāo)準(zhǔn))
24C02A 2K 5.0V CMOS serial EEPROMs(2K位,5.0V,IIC串行EEPROM)
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24C02C-EP 2K 5.0V I 2 C ⑩ Serial EEPROM
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