參數(shù)資料
型號(hào)： 28F016SA16-MBIT
廠商： Intel Corp.
英文描述： Evaluation Kit/Evaluation System for the MAX5954L/MAX5954A
中文描述： （1兆比特× 16。2兆比特× 8）FlashFile記憶
文件頁(yè)數(shù)： 16/48頁(yè)
文件大小： 304K
代理商： 28F016SA16-MBIT
SMART 3 ADVANCED BOOT BLOCK
E
16
PRELIMINARY
3.2.3
READ STATUS REGISTER
The device status register indicates when a
program or erase operation is complete and the
success or failure of that operation. To read the
status register issue the Read Status Register
(70H) command to the CUI. This causes all
subsequent read operations to output data from the
status register until another command is written to
the CUI. To return to reading from the array, issue
the Read Array (FFH) command.
The status register bits are output on DQ
0
–DQ
7
.
The upper byte, DQ
8
–DQ
15
, outputs 00H during a
Read Status Register command.
The contents of the status register are latched on
the falling edge of OE# or CE#. This prevents
possible bus errors which might occur if status
register contents change while being read. CE# or
OE# must be toggled with each subsequent status
read, or the status register will not indicate
completion of a program or erase operation.
When the WSM is active, SR.7 will indicate the
status of the WSM; the remaining bits in the status
register indicate whether or not the WSM was
successful in performing the desired operation (see
Table 7).
3.2.3.1
Clearing the Status Register
The WSM sets status bits 1 through 7 to “1,” and
clears bits 2, 6 and 7 to “0,” but cannot clear status
bits 1 or 3 through 5 to “0.” Because bits 1, 3, 4 and
5 indicate various error conditions, these bits can
only be cleared through the Clear Status Register
(50H) command. By allowing the system software
to control the resetting of these bits, several
operations may be performed (such as cumulatively
programming several addresses or erasing multiple
blocks in sequence) before reading the status
register to determine if an error occurred during that
series. Clear the status register before beginning
another command or sequence. Note, again, that
the Read Array command must be issued before
data can be read from the memory array.
3.2.4
PROGRAM MODE
Programming is executed using a two
-
write
sequence. The Program Setup command (40H) is
written to the CUI followed by a second write which
specifies the address and data to be programmed.
The WSM will execute a sequence of internally
timed events to program desired bits of the
addressed location, then Verify the bits are
sufficiently programmed. Programming the memory
results in specific bits within an address location
being changed to a “0.” If the user attempts to
program “1”s, the memory cell contents do not
change and no error occurs.
The status register indicates programming status:
while the program sequence executes, status bit 7
is “0.” The status register can be polled by toggling
either CE# or OE#. While programming, the only
valid commands are Read Status Register,
Program Suspend, and Program Resume.
When programming is complete, the Program
Status bits should be checked. If the programming
operation was unsuccessful, bit SR.4 of the status
register is set to indicate a program failure. If SR.3
is set then V
PP
was not within acceptable limits, and
the WSM did not execute the program command. If
SR.1 is set, a program operation was attempted on
a locked block and the operation was aborted.
The status register should be cleared before
attempting the next operation. Any CUI instruction
can follow after programming is completed;
however, to prevent inadvertent status register
reads, be sure to reset the CUI to read array mode.
3.2.4.1
Suspending and Resuming
Program
The Program Suspend halts the in-progress
program operation to read data from another
location of memory. Once the programming process
starts, writing the Program Suspend command to
the CUI requests that the WSM suspend the
program sequence (at predetermined points in the
program algorithm). The device continues to output
status register data after the Program Suspend
command is written. Polling status register bits
SR.7 and SR.2 will determine when the program
operation has been suspended (both will be set to
“1”). t
WHRH1
/t
EHRH1
specify the program suspend
latency.
相關(guān)PDF資料
PDF描述
28F016SV 16-MBIT (1 MBIT x 16, 2 MBIT x 8) FlashFile MEMORY
28F016SA 16-Mbit(1 Mbit x 16, 2 Mbit x 8) FlashFile Memory(16-M位(1 M位 x 16, 2 M位 x 8) FlashFile存儲(chǔ)器)
28F016XD 16-Mbit Synchronous Flash Memory(16M位DRAM接口閃速存儲(chǔ)器)
28F016XS 16-Mbit Synchronous Flash Memory(16M位同步閃速存儲(chǔ)器)
28F020 5 V Bulk Erase Flash Memory(5V 整體擦寫閃速存儲(chǔ)器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
28F016SC 制造商:未知廠家 制造商全稱:未知廠家 功能描述:28F016SC - BYTE-WIDE SmartVoltage FlashFile MEMORY FAMILY 4. 8. AND 16 MBIT
28F016SV 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:16-MBIT (1 MBIT x 16, 2 MBIT x 8) FlashFile MEMORY
28F016XD 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:16-MBIT (1 MBIT x 16) DRAM-INTERFACE FLASH MEMORY
28F016XS 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:16-MBIT (1 MBIT x 16, 2 MBIT x 8) SYNCHRONOUS FLASH MEMORY
28F0181-1SR-10 功能描述:電磁干擾濾波珠子、扼流圈和陣列 115ohms 100MHz 10A Broad Band Frequency RoHS:否 制造商:AVX 阻抗: 最大直流電流:35 mA 最大直流電阻: 容差: 端接類型:SMD/SMT 電壓額定值:25 V 工作溫度范圍:- 25 C to + 85 C 封裝 / 箱體:0603 (1608 metric)
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