參數(shù)資料
型號: 28F016SA16-MBIT
廠商: Intel Corp.
英文描述: Evaluation Kit/Evaluation System for the MAX5954L/MAX5954A
中文描述: (1兆比特× 16。2兆比特× 8)FlashFile記憶
文件頁數(shù): 18/48頁
文件大小: 304K
代理商: 28F016SA16-MBIT
SMART 3 ADVANCED BOOT BLOCK
E
18
PRELIMINARY
Table 6. Command Bus Definitions
(1, 4)
First Bus Cycle
Second Bus Cycle
Command
Notes
Oper
Addr
Data
Oper
Addr
Data
Read Array
Write
X
FFH
Read Identifier
2
Write
X
90H
Read
IA
ID
Read Status Register
Write
X
70H
Read
X
SRD
Clear Status Register
Write
X
50H
Program
3
Write
X
40H / 10H
Write
PA
PD
Block Erase/Confirm
Write
X
20H
Write
BA
D0H
Program/Erase Suspend
Write
X
B0H
Program/Erase Resume
Write
X
D0H
NOTES:
PA:
Program Address
IA:
Identifier Address
Bus operations are defined in Table 3.
Following the Intelligent Identifier command, two read operations access manufacturer and device codes. A
0
= 0 for
manufacturer code, A
0
= 1 for device code. A
1
—A
21
= 0.
Either 40H or 10H command is valid although the standard is 40H.
When writing commands to the device, the upper data bus [DQ
8
–DQ
15
] should be either V
IL
or V
IH
, to minimize current
draw.
PD:
Program Data
ID:
Identifier Data
BA:
Block Address
SRD:
Status Register Data
1.
2.
3.
4.
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