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參數(shù)資料
| 型號： | 28F032B3 |
| 廠商： | Intel Corp. |
| 英文描述： | SMART 3 ADVANCED BOOT BLOCK 4-, 8-, 16-, 32-MBIT FLASH MEMORY FAMILY |
| 中文描述： | 智能高級啟動3座4 - ，8 - ，16 - ，32 - Mbit閃存家庭 |
| 文件頁數(shù)： | 13/48頁 |
| 文件大?。?/td> | 304K |
| 代理商： | 28F032B3 |
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E
SMART 3 ADVANCED BOOT BLOCK
13
PRELIMINARY
3.1.1
READ
The flash memory has four read modes available:
read array, read identifier, read status and read
query. These modes are accessible independent of
the V
voltage. The appropriate Read Mode
command must be issued to the CUI to enter the
corresponding mode. Upon initial device power-up
or after exit from reset, the device automatically
defaults to read array mode.
CE# and OE# must be driven active to obtain data
at the outputs. CE# is the device selection control;
when active it enables the flash memory device.
OE# is the data output control and it drives the
selected memory data onto the I/O bus. For all read
modes, WE# and RP# must be at V
IH
. Figure 7
illustrates a read cycle.
3.1.2
OUTPUT DISABLE
With OE# at a logic-high level (V
), the device
outputs are disabled. Output pins are placed in a
high-mpedance state.
3.1.3
STANDBY
Deselecting the device by bringing CE# to a logic-
high level (V
) places the device in standby mode,
which
substantially
reduces
consumption without any latency for subsequent
read accesses. In standby, outputs are placed in a
high-impedance state independent of OE#. If
deselected during program or erase operation, the
device continues to consume active power until the
program or erase operation is complete.
device
power
3.1.4
DEEP POWER-DOWN / RESET
From read mode, RP# at V
IL
for time t
PLPH
deselects the memory, places output drivers in a
high-mpedance state, and turns off all internal
circuits. After return from reset, a time t
PHQV
is
required until the initial read access outputs are
valid. A delay (t
PHWL
or t
PHEL
) is required after
return from reset before a write can be initiated.
After this wake-up interval, normal operation is
restored. The CUI resets to read array mode, and
the status register is set to 80H. This case is shown
in Figure 9A.
If RP# is taken low for time t
PLPH
during a program
or erase operation, the operation will be aborted
and the memory contents at the aborted location
(for a program) or block (for an erase) are no longer
valid, since the data may be partially erased or
written. The abort process goes through the
following sequence: When RP# goes low, the
device shuts down the operation in progress, a
process which takes time t
PLRH
to complete. After
this time t
PLRH
, the part will either reset to read
array mode (if RP# has gone high during t
PLRH
,
Figure 9B) or enter reset mode (if RP# is still logic
low after t
PLRH
, Figure 9C). In both cases, after
returning from an aborted operation, the relevant
time t
PHQV
or t
PHWL
/t
PHEL
must be waited before a
read or write operation is initiated, as discussed in
the previous paragraph. However, in this case,
these delays are referenced to the end of t
PLRH
rather than when RP# goes high.
As with any automated device, it is important to
assert RP# during system reset. When the system
comes out of reset, processor expects to read from
the flash memory. Automated flash memories
provide status information when read during
program or block erase operations. If a CPU reset
occurs with no flash memory reset, proper CPU
initialization may not occur because the flash
memory may be providing status information
instead of array data. Intel’s Flash memories allow
proper CPU initialization following a system reset
through the use of the RP# input. In this application,
RP# is controlled by the same RESET# signal that
resets the system CPU.
3.1.5
WRITE
A write takes place when both CE# and WE# are
low and OE# is high. Commands are written to the
Command User Interface (CUI) using standard
microprocessor write timings to control flash
operations. The CUI does not occupy an
addressable memory location. The address and
data buses are latched on the rising edge of the
second WE# or CE# pulse, whichever occurs first.
Figure 8 illustrates a program and erase operation.
The available commands are shown in Table 6, and
Appendix A provides detailed information on
moving between the different modes of operation
using CUI commands.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 28F032C3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:3 VOLT ADVANCED+ BOOT BLOCK. 8-. 16-. 32-MBIT FLASH MEMORY FAMILY |
| 28F0330-2SR | 制造商:Steward/Laird Tech 功能描述: |
| 28F04181SR | 制造商:STEWARD 功能描述:New |
| 28F0428-0T0 | 功能描述:FERRITE FILTER 4 LINE PCB RoHS:是 類別:濾波器 >> 鐵氧體磁珠和芯片 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:EMI1812 頻率對應(yīng)阻抗:120 歐姆 @ 100MHz 額定電流:200mA DC 電阻(DCR):最大 400 毫歐 濾波器類型:差模 - 單線 封裝/外殼:1812（4532 公制） 安裝類型:表面貼裝 包裝:帶卷 (TR) 高度（最大）:0.069"（1.75mm） 尺寸/尺寸:0.177" L x 0.126" W（4.50mm x 3.20mm） 其它名稱:Q1712807A |
| 28F0430-2SR | 制造商:Laird Technologies Inc 功能描述:28F0430-2SR |
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