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參數(shù)資料
| 型號(hào)： | 30144-23 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Geode⑩ GXLV Processor Series Low Power Integrated x86 Solutions |
| 中文描述： | 32-BIT, 200 MHz, MICROPROCESSOR, PBGA352 |
| 封裝： | BGA-352 |
| 文件頁數(shù)： | 160/247頁 |
| 文件大小： | 4365K |
| 代理商： | 30144-23 |
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160
Revision 1.1
Integrated Functions (
Continued
)
G
convert the data in the VGA buffer to a separate 8-bpp
frame buffer that the hardware can use for display refresh.
The remaining modes, VGA, EGA, and VESA, can be dis-
played directly by the hardware, with no data conversion
required. For these modes, Virtual VGA often outperforms
typical VGA cards because the frame buffer data does not
travel across an external bus.
Display drivers for popular GUI (graphical user interface)
based operating systems are provided by National Semi-
conductor which enable a full featured 2D hardware accel-
erator to be used instead of the emulated VGA core.
4.6.2.1
The graphics controller contains several elements that
convert between host data and frame buffer data.
Datapath Elements
The rotator simply rotates the byte written from the host
by 0 to 7 bits to the right, based on the RotateCount field
of the DataRotate register. It has no effect in the read
path.
The display latch is a 32-bit register that is loaded on
every read access to the frame buffer. All 32 bits of the
frame buffer DWORDs are loaded into the latch.
The
write-mode unit
converts a byte from the host into a
32-bit value. A VGA has four write modes:
Write Mode 0:
- Bit n of byte b comes from one of two places,
depending on bit b of the EnableSetReset register. If
that bit is zero, it comes from bit n of the host data. If
that bit is one, it comes from bit b of the SetReset
register. This mode allows the programmer to set
some planes from the host data and the others from
SetReset.
Write Mode 1:
- All 32 bits come directly out of the display latch; the
host data is ignored. This mode is used for screen-
to-screen copies.
Write Mode 2:
- Bit n of byte b comes from bit b of the host data; that
is, the four LSBs of the host data are each replicated
through a byte of the result. In conjunction with the
BitMask register, this mode allows the programmer
to directly write a 4-bit color to one or more pixels.
Write Mode 3:
- Bit n of byte b comes from bit b of the SetReset
register. The host data is ANDed with the BitMask
register to provide the bit mask for the write (see
below).
The
read mode unit
converts a 32-bit value from the
frame buffer into a byte. A VGA has two read modes:
Read Mode 0:
- One of the four bytes from the frame buffer is
returned, based on the value of the ReadMapSelect
register. In Chain 4 mode, bits [1:0] of the read
address select a plane. In odd/even read mode, bit 0
of the read address replaces bit 0 of ReadMapSe-
lect.
Read Mode 1:
- Bit n of the result is set to 1 if bit n in every byte b
matches bit b of the ColorCompare register; other-
wise it is set to 0. There is a ColorDon
’
tCare register
that can exclude planes from this comparison. In
four-plane graphics modes, this provides a conver-
sion from 4 bpp to 1 bpp.
The ALU is a simple two-operand ROP unit that operates
on writes. Its operating modes are COPY, AND, OR, and
XOR. The 32-bit inputs are:
1) the output of the write-mode unit and
2) the display latch (not necessarily the value at the
frame buffer address of the write).
An application that wishes to perform ROPs on the source
and destination must first byte read the address (to load
the latch) and then immediately write a byte to the same
address. The ALU has no effect in Write Mode 1.
The bit mask unit does not provide a true bit mask.
Instead, it selects between the ALU output and the display
latch. The mask is an 8-bit value, and bit n of the mask
makes the selection for bit n of all four bytes of the result
(a zero selects the latch). No bit masking occurs in Write
Mode 1.
The VGA hardware of the GXLV processor does not
implement Write Mode 1 directly, but it can be indirectly
implemented by setting the BitMask to zero and the ALU
mode to COPY. This is done by the SMM code so there
are no compatibility issues with applications.
4.6.2.2
The GXLV processor core contains hardware to detect
VGA accesses and generate SMI interrupts. The graphics
pipeline contains hardware to detect and process reads
and writes to VGA memory. The VGA memory on the
GXLV processor is partitioned from system memory. The
GXLV processor has the following hardware components
to assist the VGA emulation software.
GXLV VGA Hardware
SMI Generation
VGA Range Detection
VGA Sequencer
VGA Write/Read Path
VGA Address Generator
VGA Memory
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