參數(shù)資料
型號： 73M1866B-KEYCHN
廠商： Maxim Integrated Products
文件頁數(shù)： 28/88頁
文件大?。?/td> 0K
描述： BOARD KEYCHAIN INF DANUBE EVM
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 1
73M1866B/73M1966B Data Sheet
DS_1x66B_001
34
Rev. 1.6
HOST
73M1906B
Channel 0
73M1906B
Channel 1
73M1906B
Channel 15
...
SCLK
CS
SDO
CS
SDI
SDITHRU
CID=CIDin-1
CID=CIDin-2
CIDin
CID=000
(target)
Figure 15: Daisy-Chain Configuration
The R/W bit determines whether the host requests a read (1) or a write (0) operation.
The second byte of the SPI transaction is the address byte. The address byte simply contains the 8-bit
value for the register targeted by the operation. For the 73M1x66B, only six bits of the address are
relevant for the register space, and the two most-significant bits of the address byte are always set to 0.
The third byte of the SPI transaction is the data byte. It contains the data to write to the addressed
73M1x66B registers or the data read from the addressed 73M1x66B register.
In the 8-bit mode, the three bytes are exchanged over three frames, as directed by
CS. Figure 16 and
Figure 17 show a write and read transaction between the 73M1x66B and the host in 8-bit mode.
CONTROL
ADDRESS
DATA [7:0]
SCLK
SDI
SDO
HI-Z
CS
Figure 16: SPI Write Operation – 8-bit Mode
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