參數(shù)資料
型號: 73M1866B-KEYCHN
廠商: Maxim Integrated Products
文件頁數(shù): 87/88頁
文件大?。?/td> 0K
描述: BOARD KEYCHAIN INF DANUBE EVM
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 1
73M1866B/73M1966B Data Sheet
DS_1x66B_001
88
Rev. 1.6
Revision History
Revision
Date
Description
1.0
11/7/2007
First publication.
1.1
5/13/2008
1.2
7/30/2008
1.3
11/17/2008
1.4
7/21/2009
1.5
10/16/2009
1.6
4/2/2010
Replaced Table 16 with a new table.
Replaced the schematics in Figure 12 and Figure 13 with new schematics.
Moved the steps to enable the calibration of receive DC offset from Section
8.8.3 to the 73M1866B/73M1966B Implementer’s Guide.
Corrected the Types (R, W, WO) in Table 32.
Rewrote the description of the ADJ bit.
Added clarification to the description of the PLDM bit.
Added clarification to the description of the RGDT bit.
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Teridian Semiconductor Corporation makes no warranty for the use of its products, other than expressly
contained in the Company’s warranty detailed in the Teridian Semiconductor Corporation standard Terms
and Conditions. The company assumes no responsibility for any errors which may appear in this
document, reserves the right to change devices or specifications detailed herein at any time without
notice and does not make any commitment to update the information contained herein. Accordingly, the
reader is cautioned to verify that this document is current by comparing it to the latest version on
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