參數(shù)資料
型號(hào)： 73M1866B-KEYCHN
廠(chǎng)商： Maxim Integrated Products
文件頁(yè)數(shù)： 38/88頁(yè)
文件大?。?/td> 0K
描述： BOARD KEYCHAIN INF DANUBE EVM
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 1
DS_1x66B_001
73M1866B/73M1966B Data Sheet
Rev. 1.6
43
7.5
GPIO Registers
Three user-defined I/O pins are provided in the 32-pin QFN package of the 73M1966B only. The pins are
GPIO7, GPIO6 and GPIO5.
GPIO pins are not available on the 20-pin package of the 73M1966B.
GPIO pins are not available on the 42-pin package of the 73M1866B.
Each pin can be configured independently as either an input or an output by writing to the corresponding
I/O Direction (DIR) register.
At power on and after a reset, the GPIO pins are initialized to a high impedance state to avoid unwanted
current contention and consumption. The input structures are protected from floating inputs, and no
output levels are driven by any of the GPIO pins.
The mapping of GPIO pins is designed to correspond to the bit location in their control and status
registers.
The 73M1x66B supports the ability to generate an interrupt on the
INT pin. The source can be configured
to generate on a rising or a trailing edge. Only GPIO ports that are configured as inputs can be used to
generate interrupts.
Function
Mnemonic
Register
Location
Type
Description
DIR
0x04[7:5]
W
GPIO Input/Output Select
These control bits are used to designate the GPIO pins as either
inputs or outputs.
0 = GPIO pin is defined as an output.
1 = GPIO pin is defined as an input. (Default)
GPIOn
0x03[7:5]
W
GPIO State
These bits reflect the status of the GPIO7, GPIO6 and GPIO5 pins.
If the DIR bit is reset, reading this field returns the logical value of the
appropriate GPIOn pin as an input.
If the DIR bit is set, the pins output the logical value as written.
ENGPIOn
0x05[7:5]
W
GPIO Enable
Each of the GPIO enable bits in this register enables the
corresponding GPIO bit as an edge-triggered interrupt source. If a
GPIO bit is set to one, an edge (which edge depends on the value in
the GIP register) of the corresponding GPIO pin will cause the
INT pin
to go active low, and the edge detectors will be rearmed when the
GPIO data register is read.
POLn
0x06[7:5]
W
GPIO Interrupt Edge Selection
Defines the interrupt source as being either on a rising or a falling
edge of the corresponding GPIO pin.
0 = A rising edge will trigger an interrupt from the corresponding pin.
(Default)
1 = A falling edge will trigger an interrupt from the corresponding pin.
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