參數(shù)資料
型號： 73M1866B-KEYCHN
廠商： Maxim Integrated Products
文件頁數(shù)： 59/88頁
文件大小： 0K
描述： BOARD KEYCHAIN INF DANUBE EVM
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 1
73M1866B/73M1966B Data Sheet
DS_1x66B_001
62
Rev. 1.6
Function
Mnemonic
Register
Location
Type
Description
RSTLSBI
0x0D[3]
W
Reset Line-Side Barrier Interface
To reset the Line-Side Barrier Interface, set this bit to 1.
1 = Resets the Line-Side Barrier Interface. The chip sets this bit back
to 0 after it has completed resetting the Line-Side Barrier Interface.
SLHS
0x0D[6]
R
Synchronization Lost Host Side
This bit indicates the status of the Barrier Interface as seen from the
Host-Side.
0 = Host-Side Barrier Interface is synchronized.
1 = Host-Side Barrier Interface lost synchronization.
Once read, the SLHS bit is reset, but will be set again if the
synchronization loss continues.
SLLS
0x1E[2]
R
Synchronization Loss Line Side
0 = TXRDY will continuously be generated following Synchronization
Loss so as to allow SLLS information to be transferred across the
barrier. This causes an automatic transfer of 1Eh. (Default)
1 = Synchronization is lost in the Line-Side Device due to Header.
SYNL
0x03[1]
R
Barrier Synchronization Loss
0 = Indicates synchronization of data across the barrier.
1 = Indicates a loss of synchronization of data across the barrier.
This status bit is reset when read. This is a maskable interrupt. It is
enabled by the ENSYNL bit.
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