參數(shù)資料
型號(hào): 73M2910L
廠商: Electronic Theatre Controls, Inc.
英文描述: Microcontroller
中文描述: 微控制器
文件頁(yè)數(shù): 14/35頁(yè)
文件大小: 572K
代理商: 73M2910L
73M2910L
Microcontroller
14
HDLC Control register 0 (hdlc0) sfr address 0c0H
(continued)
BITS 3,2 RXD Control
Bit 3 and bit 2 control the source of the 73M2910L RXD output pin. This output goes to the DTE’s RS232
interface. The source of this signal can be the core’s UART TXD output, the PRXD output from a modem
peripheral (clear channel), the DTE’s TXD (echo), or the value written into bit 7 of this register.
BIT 3
BIT 2
RXD OUTPUT
0
0
UART TXD Output
0
1
PRXD Buffered (clear channel)
1
0
TXD Buffered (echo)
1
1
WRXD (bit 7)
BITS 1,0 PTXD Control
Bit 1 and bit 0 control the source of the 73M2910L PTXD output pin. This output goes to the modem’s TX data
input. The source of this signal can be the core’s HDLC TX output, the DTE’s TXD output (clear channel), or the
value written into bit 6 of this register.
BIT 1
BIT 0
PTXD OUTPUT
0
0
HDLC TX Output
0
1
TXD Buffered (clear channel)
1
0
WPTXD (bit 6)
1
1
0
HDLC CONTROL REGISTER 1 (HDLC1) SFR ADDRESS 0C1h
Byte Addressable
Reset State 00h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
HDLC
RST
CCITT
CRC
PRE
RXCRC
32
RXCRC
16
TXCRC
CTRL
ZERO
ID
HDLC
INTEN
This register controls the basic set-up of the HDLC block. This register will be written during initialization and
not during normal message processing.
BIT 7 HDLC Software Reset
When bit 7 is a 1, the HDLC circuit is reset and held in a low power state and no interrupts from the HDLC
circuitry will be generated. When a 0 is written to this bit, the HDLC circuit will behave according to its control
bits.
Bit 7 and the power-on-reset signal are OR’ed together to form a reset signal for the HDLC block.
Bit 7 is cleared to a 0 upon a power-up-reset.
BIT 6 CRC Type Control
Bit 6 selects the CRC algorithm used in the 16-bit CRC calculation. There are two types of 16-bit CRCs
commonly used, CRC16 and the CCITT 16-bit CRC. If this bit is set to a 1, the CCITT type is selected.
Bit 6 is cleared to a 0 upon a reset.
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