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參數(shù)資料
| 型號： | 73M2910L |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Microcontroller |
| 中文描述： | 微控制器 |
| 文件頁數(shù)： | 20/35頁 |
| 文件大?。?/td> | 572K |
| 代理商： | 73M2910L |
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73M2910L
Microcontroller
20
HDLC INTERRUPT ENABLE REGISTER (HIE) SFR ADDRESS 0C4h
(continued)
BIT 0 Flag Detect Interrupt Enable
When bit 0 is set, a HDLC interrupt will be generated if bit 0 (FLAG DETECT) of the HDLC Status (HSTAT)
Register is also set. If bit 0 is reset to a 0, bit 2 (NEW STATUS) of the HDLC Interrupt (HINT) Register will not
be set as a result of a flag pattern detection and no HDLC interrupt will be generated.
HDLC INTERRUPT SOURCE REGISTER (HINT) SFR ADDRESS 0C5h
Byte Addressable
Read Only Register
Reset State 00h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
0
0
0
0
NEW
STATUS
RXRDY
TXRDY
This register is used to determine the source of HDLC interrupts. If one or more of these register bits are set,
the corresponding HDLC interrupt will go active if bit 0 of the HDLC Control 1 (HDLC1) Register is set to a 1.
BIT 2 New Status
When bit 2 is set, an unmasked HDLC status bit from the HDLC Status (HSTAT) Register is set.
Bit 2 will by cleared upon a reset and is cleared by a read of the HDLC Status Register.
BIT 1 RX Ready
When bit 1 is set, a new received byte has been loaded into the RX Data (RXD) Register. Note, received bits
that are flag, abort, or idle patterns are not considered data, and will not be loaded into the RX Data Register.
All inserted 0s have been removed from this byte. The RX Data Register must be read prior to the completed
reception of the next data byte.
Bit 1 will by cleared upon a reset and is cleared by a read of the RX Data Register.
BIT 0 TX Ready
Bit 0 is set if any HDLC TX control (HTXC) bits 3:0 are set as the first bit of data, flag or an idle byte is being
transmitted. While transmitting the current byte, the HDLC state machines are ready for commands pertaining
to the next byte to be transmitted. A new data byte must be loaded into the TX Data (TXD) Register to clear the
TX ready status bit.
Bit 0 will by cleared upon a reset and is cleared by writing to the TX Data Register.
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PDF描述 |
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| 73M2921 | Advanced Single Chip Modem |
| 73M2921-IG | Advanced Single Chip Modem |
| 7401 | Quad 2-Input NAND Gates with Open-Collector Outputs |
| 7404 | TRIPLE VOLTAGE REGULATOR |
| 7404 | Package contains six inverters |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 73M2910L-IG | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| 73M2921 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Advanced Single Chip Modem |
| 73M2921-IG | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Advanced Single Chip Modem |
| 73M2AR0015F | 功能描述:RES 0.0015 OHM 1% 2W 2512 制造商:cts resistor products 系列:73M2A 包裝:帶卷（TR） 零件狀態(tài):在售 電阻值:1.5 MOhms 容差:±1% 功率（W）:2W 成分:金屬薄膜 特性:電流檢測 溫度系數(shù):±100ppm/°C 工作溫度:-55°C ~ 155°C 封裝/外殼:2512（6432 公制） 供應(yīng)商器件封裝:2512 大小/尺寸:0.248" 長 x 0.126" 寬（6.30mm x 3.20mm） 高度 - 安裝（最大值）:0.043"（1.10mm） 端子數(shù):2 故障率:- 標(biāo)準(zhǔn)包裝:4,000 |
| 73M2AR001F | 功能描述:RES 0.001 OHM 1% 2W 2512 制造商:cts resistor products 系列:73M2A 包裝:帶卷（TR） 零件狀態(tài):在售 電阻值:1 MOhms 容差:±1% 功率（W）:2W 成分:金屬薄膜 特性:電流檢測 溫度系數(shù):±100ppm/°C 工作溫度:-55°C ~ 155°C 封裝/外殼:2512（6432 公制） 供應(yīng)商器件封裝:2512 大小/尺寸:0.248" 長 x 0.126" 寬（6.30mm x 3.20mm） 高度 - 安裝（最大值）:0.043"（1.10mm） 端子數(shù):2 故障率:- 標(biāo)準(zhǔn)包裝:4,000 |
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