參數(shù)資料
型號: 73M2910L
廠商: Electronic Theatre Controls, Inc.
英文描述: Microcontroller
中文描述: 微控制器
文件頁數(shù): 16/35頁
文件大?。?/td> 572K
代理商: 73M2910L
73M2910L
Microcontroller
16
HDLC CONTROL REGISTERS
(continued)
HDLC TX CONTROL REGISTER (HTXC) SFR ADDRESS 0C2h
Byte Addressable
Reset State 00h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
0
0
DIV16
CLK
SEND
ABORT
SEND
CRC
SEND
DATA
SEND
FLAG
This register is used to control the source of data that appears on the PTXD pin. Bits are shifted out on every
rising edge of the PTXCLK pin input. If no control bits are set, or more than one TX control bit is set, the PTXD
pin will go to a binary 1.
BITS 7-5 Always 0
BIT 4 16X Clock Select
Under normal synchronous operation, the PTXCLK and PRXCLK are used to receive and transmit data PRXD
and PTXD. The clock rate is equal to the data rate. In asynchronous modes, a clock 16 times the bit rate is
provided at PTXCLK and PRXCLK.
When bit 4 is set to a 1 during asynchronous operation, the clocks at the PTXCLK and PRXCLK input pins are
divided by 16 to provide transmit and receive shift clocks. An internal clock for sampling incoming PRXD data is
synchronized by detecting any edge on the PRXD data pin. The rising edge of this internal clock, used to
sample incoming data, is delayed from the falling data edge by 8 PRXCLK periods and will continue at this
phase and at a PRXCLK/16 frequency until another PRXD edge is detected.
If bit 4 is reset to a 0, the rising edge of PTXCLK is used to sample the data at PRXD, and the falling edge of
PTXCLK is used to shift new data onto PTXD.
BIT 3 Abort
When bit 3 is set to a 1, a series of consecutive ones will immediately be transmitted through the PTXD pin on
every falling edge of PTXCLK. The message will have been aborted after 2 TX ready interrupts are received.
No zeros will be inserted during the abort transmission.
BIT 2 Send CRC
When bit 2 is set, the bytes in the TX CRC generator will be inverted and serially transmitted to the PTXD
output on the falling edge on PTXCLK as soon as the present data byte transmission is completed. If bit 1 of the
HDLC Control Register is a 0, a 0 will be inserted into the CRC data stream after five consecutive ones are
transmitted. As soon as the last bit of the CRC is sent, a series of flags will be automatically sent until another
TX control bit is set. No TX ready interrupts will be generated during the transmission of the CRC bytes. A TX
ready interrupt will be generated as the first bit of each flag byte is transmitted indicating that the CRC
transmission has been completed. This should be cleared by a dummy write to the TX Data Register.
BIT 1 Send Data
When bit 1 is set, the data is the TX Data Register will be serially transmitted through the PTXD pin on every
falling edge of PTXCLK, LSB first. If bit 1 of the HDLC Control Register is a 0, a 0 will be inserted into the data
stream after five consecutive 1s are transmitted. After all eight data register bits have been sent, the HDLC will
continue to send data by loading the parallel serial transmit register with new transmit register data, unless
either a TX underrun is detected or one of the other TX control bits has been set. This bit will be cleared by the
HDLC circuitry as soon as a TX underrun is detected. A TXRDY interrupt will be generated as the first data of
each data byte is transmitted. Bit 1 will be cleared to a 0 upon a reset.
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