- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄369276 > 73M2910L (Electronic Theatre Controls, Inc.) Microcontroller PDF資料下載
參數(shù)資料
| 型號： | 73M2910L |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Microcontroller |
| 中文描述： | 微控制器 |
| 文件頁數(shù)： | 3/35頁 |
| 文件大?。?/td> | 572K |
| 代理商： | 73M2910L |
第1頁第2頁當(dāng)前第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁
73M2910L
Microcontroller
3
REGISTER DESCRIPTION
INTERRUPTS
The core chip provides 8 sources of interrupt; 3 external interrupts, 3 timer interrupts, a serial port interrupt,
and an HDLC interrupt. An external interrupt and an HDLC interrupt are unique to the 73M2910L. They do not
exist in a normal 8032 product. Previously unused bits in the IE and IP registers are now serving functions for
these additional interrupt sources. The interrupt vector addresses are as follows:
SOURCE
INT)
(IE0)
VECTOR ADDRESS
003H
TF0
INT!
(IE1)
00BH
013H
TF1
01BH
RI + TI
023H
TF2 + EXF2
INT@
- ADDED INTERRUPT
02BH
033H
HDLC - ADDED INTERRUPT
03BH
The external interrupt sources, INT(2:0), come from dedicated input pins. The apparent polarity of these pins
is individually controlled by bits in a special interrupt direction register, IDIR (address A9). The interrupt pins
INT!
and
INT)
can be either edge or level generated interrupts as indicated by bits 1 and 3 in the TCON
Register (address 88). Pin
INT@
is always an edge generated interrupt. A flag is set when a falling transition
(rising if IDIR bit 2 is set) on this pin is detected. This flag is automatically cleared when the interrupt is
processed.
INTERRUPT ENABLE REGISTER (IE) SFR ADDRESS 0A8h
Bit Addressable
Reset State 00h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
EA
EX2
ET2
ES
ET1
EX1
ET0
EX0
NOTE: Bit 6 differs from the 8032. This is a reserved bit in the 8032 and is used as a mask bit for external
interrupt 2 in the core implementation. When bit 6 is set to a 0, external interrupt 2 is disabled.
The mask bit for the HDLC interrupt source is bit 0 of the HDLC Control Register.
INTERRUPT PRIORITY REGISTER (IP) SFR ADDRESS 0B8h
Bit Addressable
Reset State 00h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
PHDLC
PX2
PT2
PS
PT1
PX1
PT0
PX0
NOTE: Bit 6 and bit 7 differ from the 8032. These are reserved bits in the 8032 and are used to determine
the priority of external interrupt 2 and the HDLC in the core implementation. When bit 6 is set to a 1,
the interrupt is set to the higher priority level.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 73M2921 | Advanced Single Chip Modem |
| 73M2921-IG | Advanced Single Chip Modem |
| 7401 | Quad 2-Input NAND Gates with Open-Collector Outputs |
| 7404 | TRIPLE VOLTAGE REGULATOR |
| 7404 | Package contains six inverters |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 73M2910L-IG | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| 73M2921 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Advanced Single Chip Modem |
| 73M2921-IG | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Advanced Single Chip Modem |
| 73M2AR0015F | 功能描述:RES 0.0015 OHM 1% 2W 2512 制造商:cts resistor products 系列:73M2A 包裝:帶卷（TR） 零件狀態(tài):在售 電阻值:1.5 MOhms 容差:±1% 功率（W）:2W 成分:金屬薄膜 特性:電流檢測 溫度系數(shù):±100ppm/°C 工作溫度:-55°C ~ 155°C 封裝/外殼:2512（6432 公制） 供應(yīng)商器件封裝:2512 大小/尺寸:0.248" 長 x 0.126" 寬（6.30mm x 3.20mm） 高度 - 安裝（最大值）:0.043"（1.10mm） 端子數(shù):2 故障率:- 標準包裝:4,000 |
| 73M2AR001F | 功能描述:RES 0.001 OHM 1% 2W 2512 制造商:cts resistor products 系列:73M2A 包裝:帶卷（TR） 零件狀態(tài):在售 電阻值:1 MOhms 容差:±1% 功率（W）:2W 成分:金屬薄膜 特性:電流檢測 溫度系數(shù):±100ppm/°C 工作溫度:-55°C ~ 155°C 封裝/外殼:2512（6432 公制） 供應(yīng)商器件封裝:2512 大小/尺寸:0.248" 長 x 0.126" 寬（6.30mm x 3.20mm） 高度 - 安裝（最大值）:0.043"（1.10mm） 端子數(shù):2 故障率:- 標準包裝:4,000 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。