參數(shù)資料
型號(hào): 73M2910L
廠商: Electronic Theatre Controls, Inc.
英文描述: Microcontroller
中文描述: 微控制器
文件頁(yè)數(shù): 19/35頁(yè)
文件大?。?/td> 572K
代理商: 73M2910L
73M2910L
Microcontroller
19
BIT 7 Transmitter Ready Interrupt Enable
When bit 7 is set, an HDLC interrupt will be generated if bit 0 (TX RDY) of the HDLC Interrupt Register is also set.
If bit 7 is reset to a 0, no HDLC interrupt indication will be given as TX RDY is set. This interrupt enable allows the
TX RDY to be a polled bit. Note that bit 5 of this register is a pre-mask to the TX RDY bit, that is, it will prevent the
TX RDY bit from ever being set.
BIT 6 Receiver Ready Interrupt Enable
When bit 6 is set, an HDLC interrupt will be generated if bit 1 (RX RDY) of the HDLC Interrupt (HINT) Register is
also set. If bit 6 is reset to a 0, no HDLC interrupt indication will be given as RX RDY is set. This interrupt enable
allows the RX RDY to be a polled bit. Note that bit 4 of this register is a pre-mask to the RX RDY bit, that is, it will
prevent the RX RDY bit from ever being set.
BIT 5 Transmit Ready Enable
Bit 5 is used to enable the TX RDY and TX underrun interrupt sources. When bit 5 is set, the transmitter ready
indication will set bit 0 of the HDLC Interrupt Register. The TX RDY indication will go active as the first bit of a
message byte is being transmitted, except during CRC transmission. Also, if this bit is set, the TX underrun
condition will result in a new status interrupt. If bit 5 is reset to a 0, bit 0 of the HDLC Interrupt Register will not be
set, and no corresponding HDLC interrupt will be generated. Also, a TX underrun condition, as indicated by bit 5
of the HDLC Status Register, will not result in an HDLC interrupt or in setting the new status interrupt bit.
BIT 4 Receiver Ready Enable
Bit 4 is used to enable the RX RDY and RX overrun interrupt sources. When bit 4 is set, the receiver ready
indication will set bit 1 of the HDLC Interrupt (HINT) Register. The RX RDY indication will go active when a data
byte (a byte that is not a flag, idle, or an abort pattern) is loaded into the RX Data Register. Also, if this bit is set,
the RX overrun condition will result in a new status interrupt. If bit 4 is reset to a 0, bit 1 of the HDLC Interrupt
Register will not be set, and no corresponding HDLC interrupt will be generated. Also, a RX overrun condition, as
indicated by bit 4 of the HDLC Status (HSTAT) Register, will not result in a HDLC interrupt or in setting the new
status interrupt bit.
BIT 3 Invalid Flag Interrupt Enable
When bit 3 is set, a HDLC interrupt will be generated if bit 3 (INVALID FLAG) of the HDLC Status (HSTAT)
Register is also set. If bit 3 is reset to a 0, bit 2 (NEW STATUS) of the HDLC Interrupt (HINT) Register will not be
set as a result of an invalid flag boundary detection and no HDLC interrupt will be generated.
BIT 2 Abort Detect Interrupt Enable
When bit 2 is set, a HDLC interrupt will be generated if bit 2 (ABORT DETECT) of the HDLC Status (HSTAT)
Register is also set. If bit 2 is reset to a 0, bit 2 (NEW STATUS) of the HDLC Interrupt (HINT) Register will not be
set as a result of an abort pattern detection and no HDLC interrupt will be generated.
BIT 1 Idle Detect Interrupt Enable
When bit 1 is set, an HDLC interrupt will be generated if bit 1 (IDLE DETECT) of the HDLC Status (HSTAT)
Register is also set. If bit 1 is reset to a 0, bit 2 (NEW STATUS) of the HDLC Interrupt (HINT) Register will not be
set as a result of an idle pattern detection and no HDLC interrupt will be generated.
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