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參數(shù)資料
| 型號： | 78Q8430-100IGTR/F |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 41/88頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LAN MEDIA ACCESS CTLR 100LQFP |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 1,000 |
| 控制器類型： | 以太網控制器，MAC/PHY |
| 電源電壓： | 3.3V |
| 電流 - 電源： | 230mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應商設備封裝： | 100-LQFP（14x14） |
| 包裝： | 帶卷 (TR) |
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78Q8430 Data Sheet
DS_8430_001
46
Rev. 1.2
1. After the second attempt, r is a random number between 0 and 3; the state machine looks at the two
least significant bits of the generator (n = 2) which gives a value between 0 and 3.
In order to improve the statistical independence between two MACs using the same pseudo-random
number generator, the MAC uses values from the CRC of previous successfully transmitted packets to
modify the basic random number sequence.
6.10.6 Transmit Operation
If there is data to be transferred, the inter-packet gap is OK and the MII is ready (there are no collisions
and the device is either in full duplex mode or there is no CRS), then the MAC transmit block transmits
the preamble followed by the SFD. After the transmission of the preamble and the SFD, it transmits 64
bytes of data regardless of the packet length, unless short transmission is enabled. This means that if the
packet is less than 64 bytes, it will pad the LLC data field with zeroes, unless NoPad is enabled. At the
end of the packet, it appends the CRC, unless NoCRC generation is enabled. If there is any collision
during the first 64 bytes (8 bytes of preamble and SFD and 56 bytes of the frame), it stops the
transmission and transmits a jam pattern (32 bits of all ones). It increments the collision attempt counter,
returns control to the back-off state machine and retransmits the packet when the back-off time has
elapsed and the gap time is OK.
If there is a collision after the first 64 bytes, it is reported as a late collision and the packet is terminated
with an error indication. The 78Q8430 does not retry late collisions.
If there are no collisions, the MAC transmit block transmits the rest of the packet and at this time (after the
first 64 bytes have been transmitted without collisions), it allows the DMA engine to overwrite this packet.
After transmitting the first 64 bytes, it transmits the rest of the packet and appends the CRC to the end.
FIFO under-run or more than 16 collisions will cause the state machine to abort the packet (no retry) and
prepare for the next packet in the queue.
In case of any transmission errors, the MAC transmit block sets the appropriate error bit in the TPSR and
sends a bad TX signal to the interrupt controller.
6.10.7 Receiving a Frame
To receive a frame, the receive enable bit in the MCR must be set and the receive halt bit must be clear.
The MAC receive block, when enabled, constantly monitors a data stream coming from the integrated
PHY. If the MAC is in loop back mode, the data stream will be going to the MAC transmit block via
internal connections.
The MAC receive block receives zero to seven bytes of preamble, followed by the Start Frame Delimiter
(SFD). The MAC receive block checks that the first data received is preamble and looks for the SFD in
the first eight bytes. If the SFD is not the first non-preamble byte, it treats the packet as a fragment and
discards it. When it has received a full byte, the MAC receive block stores the byte and several status
bits in the MAC receive FIFO which then signals that data is present. It receives subsequent bytes and
stores them and their status in the FIFO. If, during the frame reception, the receive FIFO overflows, or
the PHY asserts mii_rx_er, or the frame ends on an odd nibble, the MAC receive block sets the
corresponding status bit for the byte in the FIFO.
The QUE receive controller reads bytes from the MAC receive FIFO, combines them into four-byte words,
checks the CRC, optionally drops the padding and/or CRC field and moves the data into the receive
QUE. The QUE receive controller will never take bytes from the FIFO on two consecutive clocks. The
status bits from the receive FIFO are held by the QUE receive controller for the receive status FIFO until
the EOF status bit from the FIFO is true, at which time the final status is added to the status FIFO and the
held status bits are all cleared in preparation for the next frame. The QUE receive controller will signal
the receive producer to drop a frame if there is no room in the status FIFO when the frame arrives. This
makes sure that there is a one-to-one relation between frames in the QUE and status words in the status
FIFO.
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