參數(shù)資料
型號(hào)： 78Q8430-100IGTR/F
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 74/88頁(yè)
文件大?。?/td> 0K
描述： IC LAN MEDIA ACCESS CTLR 100LQFP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 1,000
控制器類型： 以太網(wǎng)控制器，MAC/PHY
電源電壓： 3.3V
電流 - 電源： 230mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-LQFP（14x14）
包裝： 帶卷 (TR)
78Q8430 Data Sheet
DS_8430_001
76
Rev. 1.2
7.7.3
PHY Status Register – MR1
MR1 bits 15 through 11 reflect the ability of the 78Q8430 PHY. They do not reflect any ability changes
made via the MII Management interface to MR0 bits 13 (SPEEDSL), 12 (ANEGEN) and 8 (DUPLEX).
Bits
Symbol
Type
Default Description
15
100T4
R
0
100BASE-T4 Ability
Reads 0 to indicate the 78Q8430 PHY does not support
100BASE-T4 mode.
14
100X_F
R
1
100BASE-TX Full Duplex Ability
0 = Not able
1 = Able (default)
13
100X_H
R
1
100BASE-TX Half Duplex Ability
0 = Not able
1 = Able (default)
12
10T_F
R
1
10BASE-T Full Duplex Ability
0 = Not able
1 = Able (default)
11
10T_H
R
1
10BASE-T Half Duplex Ability
0 = Not able
1 = Able (default)
10
100T2_F
R
0
100BASE-T2 Full Duplex Ability
Reads 0 to indicate the 78Q8430 PHY does not support
100BASE-T2 full duplex mode.
9
100T2_H
R
0
100BASE-T2 Half Duplex Ability
Reads 0 to indicate the 78Q8430 PHY does not support
100BASE-T2 half duplex mode.
8
EXTS
R
0
Extended Status Information Availability
Reads 0 to indicate the 78Q8430 PHY does not support
Extended Status information in MR15.
7
RSVD
R
0
Reserved
6
MFPS
R
0
Management Frame Preamble Suppression Support
A 0 indicates that the 78Q8430 PHY can read management
frames with a preamble.
5
ANEGC
R
0
Auto-negotiation Complete
Logic one indicates that the auto-negotiation process has
been completed and that the contents of registers MR4, 5, 6
are valid.
4
RFAULT
RC/LH
0
Remote Fault
A logic one indicates that a remote fault condition has been
detected and when so, it remains set until it is cleared. This
bit can only be cleared by reading this register (MR1) via the
management interface.
3
ANEGA
R
(1)
Auto-negotiation Ability
When set, this bit indicates the device’s ability to perform
Auto-Negotiation. The value of this bit is determined by the
2
LINK
RC/LL
0
Link Status
A logic one indicates that a valid link has been established. If
the link status should transition from an OK status to a NOT-
OK status, this bit will become cleared and remains cleared
until it is read.
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