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參數(shù)資料
| 型號(hào)： | 78Q8430-100IGTR/F |
| 廠(chǎng)商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 73/88頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC LAN MEDIA ACCESS CTLR 100LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 控制器類(lèi)型： | 以太網(wǎng)控制器，MAC/PHY |
| 電源電壓： | 3.3V |
| 電流 - 電源： | 230mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-LQFP（14x14） |
| 包裝： | 帶卷 (TR) |
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DS_8430_001
78Q8430 Data Sheet
Rev. 1.2
75
7.7.2
PHY Control Register – MR0
Bits
Symbol
Type
Default Description
15
RESET
R/WC
0
Reset
Setting this bit to 1 resets the device and sets all registers to
the default states. This bit is self-clearing.
14
LOOPBK
R/W
0
Loopback
When this bit is set to 1, input data at TXD[3:0] is output at
RXD[3:0]. No transmission of data on the network medium
occurs and receive data on the network medium is ignored.
By default, the loopback signal path encompasses most of the
digital functional blocks. This bit allows for diagnostic testing.
13
SPEEDSL
R/W
1
Speed Selection
This bit determines the speed of operation of the 78Q8430
PHY. Setting this bit to 1 indicates 100Base-TX operation and
a 0 indicates 10Base-T mode. This bit will default to 1 upon
reset. When auto-negotiation is enabled, this bit will not be
writable and will have no effect on the 78Q8430 PHY. If
auto-negotiation is not enabled, this bit may be written to force
manual configuration.
12
ANEGEN
R/W
1
Auto-negotiation Enable
The auto-negotiation process is enabled by setting this bit to 1.
This bit will default to 1. If this bit is cleared to 0, manual speed
and duplex mode selection is accomplished through bit 13
(SPEEDSL) and bit 8 (DUPLEX) of the MR0 Control Register.
11
PWRDN
R/W
0
Power-down
The device may be placed in a low power consumption state
by setting this bit to 1. While in the power-down state, the
device will still respond to management transactions.
10
RSVD
R
0
Reserved
9
RANEG
R/WC
0
Restart Auto-negotiation
Normally, the Auto-Negotiation process is started at power up.
The process can be restarted by setting this bit to 1. This bit
is self-clearing.
8
DUPLEX
R/W
1
Duplex Mode
This bit determines whether the device supports full- duplex or
half duplex. A 1 indicates full duplex operation and a 0
indicates half duplex. This bit will default to 1 upon reset.
When auto-negotiation is enabled, this bit will not be writable
and will have no effect on the 78Q8430 PHY. If
auto-negotiation is not enabled, this bit may be written to force
manual configuration.
7
COLT
R/W
0
Collision Test
When this bit is set to 1, the device will assert the COL signal
in response to the assertion of the TX_EN signal. Collision
test is disabled if the PCSBP bit, MR16[1], is high. The
Collision test can be activated regardless of the duplex mode
of operation.
6:0
RSVD
R
0
Reserved
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