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參數(shù)資料
| 型號： | 78Q8430-100IGTR/F |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 53/88頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LAN MEDIA ACCESS CTLR 100LQFP |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 1,000 |
| 控制器類型： | 以太網(wǎng)控制器，MAC/PHY |
| 電源電壓： | 3.3V |
| 電流 - 電源： | 230mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-LQFP（14x14） |
| 包裝： | 帶卷 (TR) |
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DS_8430_001
78Q8430 Data Sheet
Rev. 1.2
57
7.5.3
Setup Transmit Data Register
Name: STDR
Reset Val: 0x0000_0000
Block: QUE
Address: 0x008
Bits
Type
Default
Description
31:25
X
Reserved
24
RW
Endian
The network transmit byte order.
Set = big endian (Most significant byte transmit first)
Clear = little endian (Least significant byte transmit first)
23:20
X
Reserved
19:18
RW
00
Start Offset
The number of bytes to ignore on the first data word written for this
buffer. This byte mask is applied any time the Count value is
non-zero. After each time it is applied, however, it is reset to zero such
that it is really only applied on the first write.
17:16
RW
00
End Offset
The number of bytes to ignore on the last data word written for this
buffer. This byte mask is applied any time the Count value is zero.
Unlike the Start Offset, the End Offset is not self clearing. This means
that the End Offset will be applied to all writes to the QUE once the
Count value reaches zero, unless the host clears the End Offset. The
remainder of PSZR will override the End Offset when a write occurs
and the PSZR value is less than four.
15:14
X
Reserved
13:0
RW
0000
Count
The total number of writes needed to complete the buffer minus one.
This counter decrements on each write operation to the QUE. This
counter decrements on each write operation to the QUE until it reaches
zero. The Count value will remain zero until the next host write. The
value written here must be one less than the number of writes in the
buffer so that the Count value will equal zero on the last write and
cause the End Offset to be applied.
7.5.4
Transmit Data Register
Name: TDR
Reset Val: 0x0000_0000
Block: QUE
Address: 0x00C
Bits
Type
Default
Description
31:0
WO
N/A
Packet Data to Add to the QUE
Data written to this register is added to the QUE to which the register
belongs.
7.5.5
Receive Data Register
Name: RDR
Reset Val: 0x0000_0000
Block: QUE
Address: 0x010
Bits
Type
Default
Description
1:0
RO
N/A
Packet Data Read from the QUE
Data read from this register is shifted out of the QUE to which the
register belongs. The RPSR should be consulted to make sure data is
available before reading this register.
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