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參數(shù)資料
| 型號： | 78Q8430-100IGTR/F |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 43/88頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LAN MEDIA ACCESS CTLR 100LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 控制器類型： | 以太網(wǎng)控制器，MAC/PHY |
| 電源電壓： | 3.3V |
| 電流 - 電源： | 230mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-LQFP（14x14） |
| 包裝： | 帶卷 (TR) |
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78Q8430 Data Sheet
DS_8430_001
48
Rev. 1.2
6.11.1.5 Signal Quality Error
In 10 Mbps mode, the MAC checks for a “heartbeat” at the end of a transmitted packet. This is a short
Collision signal within the first 40 bit times after end of transmission. Signal Quality Error sets the No
Heart Beat bit in the Transmit Packet Status Register (TPSR).
6.11.1.6 Deferral
In half duplex mode, during any attempt to send a packet, the MAC may have to defer the transmission
because of a pre-occupied network. This is not an error, but is used as a network activity indicator, but
only when collisions do not occur. Deferral sets the Deferral bit of the Transmit Packet Status Register
6.11.1.7 Excessive Deferral
In half duplex operation, the MAC will defer transmission of frames when there is network activity. If the
deferral time is longer than two maximum sized frame times (2.4288 ms for 10-Mbps operation or 0.24288
ms for 100-Mbps operation) then the Excessive Deferral bit of the Transmit Packet Status Register
(TPSR) is set. If the Tx Enable bit of the MCR Register (MCR) is clear, then the transmission is aborted.
Excessive deferral indicates a possible network problem.
6.11.2 MAC Receive Errors
6.11.2.1 Alignment Error
At the end of reception, the MAC receive block checks that the incoming packet has been correctly
framed on an 8-bit boundary. If it is not and the CRC is invalid, data has been disrupted through the
network and the MAC receive block reports an alignment error. A CRC error is also reported. The
Dangling Byte bit and the CRC bit are set in the Receive Packet Status Register (RPSR).
6.11.2.2 CRC Error
At the end of reception, the MAC receive block checks the CRC for validity and reports a CRC error if it is
invalid.
6.11.2.3 Overflow Error
During reception, incoming data is put into the MAC receive FIFO before it is transferred to the QUE
receive controller. If the MAC receive FIFO fills up because of excessive system latency or other
reasons, the MAC receive block sets the Overflow Error of the Receive Packet Status Register (RPSR)
and the remaining frame is dropped.
6.11.2.4 Length Error
The MAC receive block checks the length of the incoming packet at the end of reception based on the
value of the Len/Type field of the frame. If the length is specified in the Len/Type field and the frame is
longer than the maximum frame size of 1518 bytes, (1522 for VLAN tagged packets), the MAC receive
block reports a length error, unless long frame mode is enabled. The MAC will also flag as an error a
MAC control frame that is not exactly 64 bytes in length.
6.11.2.5 MII Error
The PHY informs the MAC if it detects a media error (such as coding violation) by asserting RX_ER.
When the PHY asserts RX_ER, the MAC sets the MII error bit in the Receive Packet Status Register
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