參數(shù)資料
型號: 78Q8430EBST#DB
廠商: Maxim Integrated Products
文件頁數(shù): 13/88頁
文件大?。?/td> 0K
描述: EVAL BOARD 78Q8430
標(biāo)準(zhǔn)包裝: 1
系列: *
78Q8430 Data Sheet
DS_8430_001
20
Rev. 1.2
4.5.3
100Base-TX Receiver
Table 18: MII 100Base-TX Receiver Timing
Parameter
Conditions
Min
Nom
Max
Unit
Signal Detect Assertion Threshold
600
700
800
mVppd
Signal Detect De-assertion Threshold
300
350
400
mVppd
Differential Input Resistance
20
k
Jitter Tolerance (pk-pk)
4
ns
Baseline Wander Tracking
-75
+75
%
Signal Detect Assertion Time
Not tested
1000
s
Signal Detect De-assertion Time
Not tested
4
s
4.5.4
10Base-T Transmitter
Table 19: MII 10Base-T Transmitter Timing
Parameter
Conditions
Min
Nom
Max
Unit
Peak Differential Output Signal
(see note below)
All data patterns
2.2
2.8
V
Harmonic Content
(dB below fundamental)
Any harmonic
All ones data
Not tested
27
dB
Link Pulse Width
100
ns
Start-of-Idle Pulse Width
Last bit 0
Last bit 1
300
350
ns
Note: The Manchester-encoded data pulses, the link pulse and the start-of-idle pulse are tested against
the templates and using the procedures found in Clause 14 of IEEE 802.3. Measured at the line side of
the transformer. Test Condition: Transformer P/N: TLA-6T103. Line Termination: 100
Ω±1%
4.5.5
10Base-T Transmitter (Informative)
Table 20: MII 10Base-T Transmitter (Informative)
Parameter
Conditions
Min
Nom
Max
Unit
Output Return Loss
15
dB
Output Impedance Balance
1 MHz < freq < 20 MHz
29
17
10
log
f
dB
Peak Common-mode Output Voltage
50
mV
Common-mode Rejection
15 VPK
, 10.1 MHz sine
wave applied to transmitter
common-mode. All data
sequences.
100
mV
Common-mode Rejection Jitter
15 VPK
, 10.1 MHz sine
wave applied to transmitter
common-mode. All data
sequences.
1
ns
Note: The specifications in the preceding table are included for information only. They are mainly a
function of the external transformer and termination resistors used for measurements
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