參數(shù)資料
型號(hào)： 78Q8430EBST#DB
廠商： Maxim Integrated Products
文件頁數(shù)： 71/88頁
文件大?。?/td> 0K
描述： EVAL BOARD 78Q8430
標(biāo)準(zhǔn)包裝： 1
系列： *
DS_8430_001
78Q8430 Data Sheet
Rev. 1.2
73
Name: HIR
Reset Val: 0x0000_0000
Block: CTL
Address: 0x1E8
Bits
Type
Default
Description
6
RO
0
Reserved.
5
RO
0
Late Tx Notify
Interrupt on completion. (See PCWR)
4
RO
0
Early Tx Notify
Interrupt at the start of transmission. (See PCWR)
3
RO
0
WATER MARK
Interrupt when the free BLOCK count hits the low water mark.
2
RO
0
QUE Overflow
Interrupt when a QUE requests memory and there is none.
1
RO
0
PAUSE
Interrupt when the local pause changes state (on/off).
0
RO
0
Class
Packet classification interrupt.
Note: Bits 15:0 are cleared on read. Bits 31:16 are only cleared when the source is cleared.
7.6.42 Host Interrupt Mask Register
Name: HIMR
Reset Val: 0x0000_0000
Block: CTL
Address: 0x1EC
Bits
Type
Default
Description
31:0
RW
Host Interrupt Mask
When a bit is set here it enables the host interrupt for the corresponding
bit in the HIR. When a bit is clear here, the corresponding bit in the HIR
will still be set on its event and cleared on read but will not trigger an
interrupt on
INT.
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