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| 型號(hào)： | 78Q8430EBST#DB |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 19/88頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | EVAL BOARD 78Q8430 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
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78Q8430 Data Sheet
DS_8430_001
26
Rev. 1.2
MII
Transmit
Logic
4B/5B Encoder
Scrambler,
Parallel to Serial
100M
NRZ/NRZI
MLT3 Encoder
Pulse Shaper
and Filter
Parallel to Serial
Manchester
Encoder
Tx Clock
Generator
UTP
Driver
TXOP
TXON
UTP
Receiver
RXIP
RXIN
LED0
LED1
Auto
Negotiation
Clock
Recovery
Carrier Sense,
Collosion Detect
10M
Serial to Parallel
Descrambler,
5B/4B Decoder
Manchester
Decoder,
Serial to Parallel
100M
Clock
Reference
XTLP/CLKIN
XTLN
VCC
GND
MII
Receive
Logic
MII
Activity
MII
Registers
Interrupt
Logic
10M
Adaptive Equalizer,
Baseline Wander,
MLT3 Decoder,
NRZI/NRZ
LED
Control
Logic
LINK
TXA
RXA
COLI
100BT
10BT
FDX
TX_CLK
TXD[3:0]
TX_EN
TX_ER
INTR
CRS
COL
RX_CLK
RXD[3:0]
RX_DV
RX_ER
MDC
MDIO
Figure 13: Internal PHY Block Diagram
On the right side are the signals, which connect to the status LEDs and a 1:1 isolation transformer before
connecting to an RJ-45 connector, or equivalent media components.
6.2
Data Queuing
Ethernet frame data in the 78Q8430 is managed in queuing structures called QUEs. The host bus
address space allocated for QUEs has enough space for eight, while the 78Q8430 circuit only
implements five. QUEs are identified numerically, QUE0 through QUE7, based on the registers in the
QUE register space that are used to access them. QUE1, QUE6 and QUE7 are unimplemented and
reserved for future use.
A QUE allocates main buffer memory as needed and stores discrete frames as they are written into the
QUE. The QUE then reads back frames in the same order that they were written and frees the main
buffer memory. A QUE can contain a maximum of 125 frames at any one time. If a QUE is unable to
allocate main buffer memory when writing a frame, the frame will be partially added to the QUE as a
truncated frame. If a QUE is unable to allocate main buffer memory to start a frame, the entire frame is
dropped.
The QUEs are divided into two categories: receive QUEs, that store received frame data and transmit
QUEs, that store transmit frame data. Frames are written to a receive QUE by the MAC and read out by
the host. Frames are written to a transmit QUE by the host and read out by the MAC. QUE0 and QUE1
are receive QUEs (only QUE0 is implemented), and QUE2 through QUE7 are transmit QUEs (QUE2
through QUE5 are implemented). Writing to the Transmit Data Register (TDR) for a receive QUE or
reading from the Read Data Register (RDR) for a transmit QUE is not supported and the result is
undefined in this specification.
The transmit QUEs are further divided into standard QUEs, as described above, and static QUEs. Static
QUEs differ from the standard QUEs in that they can only contain a single frame, and that frame must be
252 bytes or less in total size. Unlike standard QUEs, static QUEs do not remove a frame when it is read
from the QUE. Once a frame is written to a static QUE, it can be read out any number of times and the
static QUE will always read out the same one frame. If a second frame is written to a static QUE then it
will replace the first as the one frame contained in the QUE.
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