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參數(shù)資料
| 型號(hào)： | 78Q8430EBST#DB |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 70/88頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVAL BOARD 78Q8430 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
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78Q8430 Data Sheet
DS_8430_001
72
Rev. 1.2
7.6.38 Transmit RMON Mask Register
Name: TRMR
Reset Val: 0x0000_0000
Block: CTL
Address: 0x1D4
Bits
Type
Default
Description
31:0
RW
0x0000
0000
Tx RMON Interrupt Mask
When a bit is set, it enables the Tx RMON interrupt for the
corresponding bit in the TRIR. When a bit is clear, the corresponding
bit in the TRIR will still be set on its event and cleared on read but will
not be passed on to the HIR.
7.6.39 Receive RMON Interrupt Register
Name: RRIR
Reset Val: 0x0000_0000
Block: CTL
Address: 0x1D8
Bits
Type
Default
Description
31:0
RO
0x0000
0000
RMON Rx Counter Rollover
Set when the RMON Rx counter with an index equal to the bit number
plus 32 has rolled over.
Note: All bits are cleared on read.
7.6.40 Receive RMON Mask Register
Name: RRMR
Reset Val: 0x0000_0000
Block: CTL
Address: 0x1DC
Bits
Type
Default
Description
31:0
RW
0x0000
0000
Rx RMON Interrupt Mask
When a bit is set, it enables the Rx RMON interrupt for the
corresponding bit in the RRIR. When a bit is clear, the corresponding
bit in the RRIR will still be set on its event and cleared on read but will
not be passed on to the HIR.
7.6.41 Host Interrupt Register
Name: HIR
Reset Val: 0x0000_0000
Block: CTL
Address: 0x1E8
Bits
Type
Default
Description
31:21
X
0x000
Reserved
20
RO
0
WAKE
PME is asserted low (a power event has occurred).
19
RO
0
QUE Status
QSIR interrupt.
18
RO
0
QUE Overflow/Underrun
OUIR interrupt.
17
RO
0
PHY
16
RO
0
RMON
15:13
X
0
Reserved
12
RO
0
Tx Bad
A transmitted frame had an error.
11
RO
0
Rx Bad
A frame was received with an error.
10:9
X
Reserved
8
RO
0
Late Rx Notify
This interrupt is asserted each time an entire frame is added to the
receive QUE.
7
RO
0
Early Rx Notify
Data reception has started (delayed by the IDCR).
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