
DS_8430_001
78Q8430 Data Sheet
Rev. 1.2
27
The purpose of a static transmit QUE is to allow the host to configure a frame that will need to be
transmitted multiple times or transmitted at a later time without any interaction with the host. Transmit
QUE2 and QUE5 are static QUEs. Transmit QUE2 is best suited for MAC control pause frames as it can
be triggered to transmit by a main buffer watermark. Transmit QUE5 is best suited to
Host NotResponding (HNR) frames as it can be triggered to transmit by a host interrupt timeout.
When the MAC transmitter is idle and ready to transmit a frame, it determines which QUE to read from on
a priority basis. The lowest numbered QUE containing data that needs to be transmitted is selected by
the MAC, which means when more than one transmit QUE is ready, the one with the lowest number
always gets priority.
6.3
Host Interface
6.3.1
Reading Receive Data
The status of the frame at the top of the receive FIFO can be obtained by reading the
Receive Packethave entered the receive FIFO for this frame. A value of zero means that there are no new frames in the
receive FIFO. As frame bytes enter the FIFO, the count value is incremented. However, the count value
does not decrease the bytes read out of the read FIFO such that the final value will always be the final
frame size.
The MSB of the
RPSR is the
DONE bit. Once the last byte in the frame has entered the receive FIFO,
the
DONE bit is set indicating that the count value contained in the total bytes field now contains the final
size in bytes of the frame and the error status and classification fields now contain the final frame status.
When the
DONE bit is asserted, this also indicates that the status for this frame has been removed from
the receive status FIFO and future reads of the
RPSR will refer to the next frame in the receive FIFO,
even if all of the data for the current frame has not been retrieved.
The frame data is read from the receive FIFO 32 bits at a time by successive reads to the
Receive DataRegister (RDR). If the frame length is not an even multiple of 4 bytes then the final read of the RPDR
register for that frame will be padded with zeros.
6.3.2
Writing Transmit Data
ID to the frame and select various transmission options. The frame size must then be set by writing to the
If more bytes are written to the TDR than indicated n the PSZR, the excess bytes are ignored. Writes to
the
TDR past the end of the frame, however, will trigger a transmit FIFO overrun interrupt condition.
Similarly, if a new frame is initialized by a write to the
PCWR before the frame length counter is expired, a
transmit FIFO under-run interrupt condition will result and the previous frame will be aborted. If there is
any question, the
PSZR can be queried for the remaining number of bytes expected in the previous frame
before a new frame is initialized.
In the event that the host wishes to terminate a frame early without triggering an under-run interrupt and
aborting the frame, or if the size of the frame is not initially known, the
PSZR can be rewritten at any time
before the end of the frame’s transmission. As an example, no matter what the current value of the
PSZRis, if it is written with a value of one then the next write to the
TDR will add one byte to the completed
frame. Conversely, if the frame byte counter is about to expire then writing a larger value to the
PSZR will
extend the frame. It is an error to write a value of zero to the
PSZR and the circuit behavior in this case is
undefined.
As each frame egresses the transmit FIFO, its status is placed in the transmit status FIFO. Transmit
from the
PCWR is also placed in the
TPSR such that the status can be associated with the exact frame to
which it belongs.