IDT Table of Contents
79RC32438 User Reference Manual
v
November 4, 2002
Notes
Interrupt Status Description.........................................................................................................8-4
Non-Maskable Interrupts.............................................................................................................8-6
Non-Maskable Interrupt Pin Status Register......................................................................8-7
9 DMA Controller
Introduction..................................................................................................................................9-1
Features.......................................................................................................................................9-1
DMA Registers.............................................................................................................................9-1
Data Flow within the RC32438....................................................................................................9-3
The IPBus.......................................................................................................................9-3
4Kc Core as Bus Master....................................................................................................9-3
DMA Controller...................................................................................................................9-4
No Alignment Restrictions..................................................................................................9-4
Data Flow Using the DMA Controller.................................................................................9-5
Memory-to-Memory Transfer..............................................................................................9-5
DMA Channels.............................................................................................................................9-6
Internal DMA Operation...............................................................................................................9-7
DMA Descriptor Register....................................................................................................9-8
DMA Registers...................................................................................................................9-9
DMA Stopping Conditions..................................................................................................9-9
DMA Request Event.........................................................................................................9-10
DMA Descriptor List and Chaining...................................................................................9-10
DMA [0..9] Control Register.............................................................................................9-12
DMA [0..9] Status Register...............................................................................................9-13
DMA [0..9] Status Mask Register.....................................................................................9-14
DMA [0..9] Descriptor Pointer Register............................................................................9-15
DMA [0..9] Next Descriptor Pointer Register....................................................................9-15
External DMA Operations..........................................................................................................9-16
Device Control and Status Field for External DMA..........................................................9-16
Device Command Field for External DMA........................................................................9-16
Memory to Memory DMA Operations........................................................................................9-19
Examples...................................................................................................................................9-20
10 PCI Bus Interface
Introduction................................................................................................................................10-1
Features.....................................................................................................................................10-1
Use of Decoupled PCI Transactions..........................................................................................10-2
IPBus Access.............................................................................................................................10-2
PCI Register Description ...........................................................................................................10-3
PCI Control Register........................................................................................................10-4
PCI Status Register..........................................................................................................10-7
PCI Status Mask Register..............................................................................................10-10
Reset.......................................................................................................................................10-13
Disabled Mode.........................................................................................................................10-14
PCI Host Mode ........................................................................................................................10-14
Reset and Initialization...................................................................................................10-14
Bus Arbitration................................................................................................................10-14