IDT EJTAG System
EJTAG Test Access Port
79RC32438 User Reference Manual
20 - 72
November 4, 2002
Notes
4. A reset of the processor occurs, the Rocc bit is set, and the PrAcc bit is cleared.
5. A new processor access occurs, because EJTAGBOOT was indicated.
6. A write of the EJTAG Control register is attempted with PrAcc equal to 0 and Rocc equal to 1, but
the write does not occur because the Rocc bit is set. The new processor access that was not seen
is not finished.
7. Polling of the EJTAG Control register continues. The probe detects that the Rocc bit is set.
8. The probe writes the EJTAG Control register with Rocc equal to 0 to acknowledge that the probe has
seen the reset.
9. The new processor access is serviced as usual.
Inhibiting writes to the EJTAG Control register because of the Rocc bit ensures that the new processor
access is not finished by mistake due to detection of a pending processor access before the reset occurred.
EJTAG Memory Access Through Processor Access
The processor access feature makes it possible for the probe to handle accesses from the processor to
the specific EJTAG memory area (dmseg). The processor can execute a debug handler from EJTAG
memory, whereby applications that are not prepared with EJTAG code in the system memory can still be
debugged. The probe can get information about the access through the TAP, as shown in Table 20.52.
The servicing of processor accesses works with a polling scheme, where the PrAcc bit is polled until a
pending processor access is indicated by PrAcc equal to 1. Then the Address register is read to get the
address of the transaction, and the Data register is accessed to get the write data or provide the read data.
Finally the PrAcc bit is cleared, in order to finish the access from the processor.
In addition, the ProbTrap and ProbEn bits control the debug exception vector location and the indication
to the processor that the probe will service accesses to the EJTAG memory through processor accesses.
Handling of processor access in relation to reset requires specific handling. A pending processor access is
cleared at reset. At the same time, the Rocc bit is set, thereby inhibiting any processor accesses to be
finished until Rocc is cleared. Thus, the probe will have to acknowledge that a reset occurred, preventing it
from accidentally finishing a processor access that occurred before the reset. A pending processor access
can only finish if the probe clears PrAcc or a processor reset occurs.
The width of the Address register is 32 to 64 bits. The specific length is determined by shifting a known
bit pattern through the register. The following sections show examples of servicing read and write processor
accesses.
Write Processor Access
Figure 20.35 shows a possible flow for servicing a write processor access. The example implements a
32-bit processor with 32-bit Address register, running in little-endian mode. A halfword store is performed to
address 0xFF20 1232 of value 0x5678.
Information
Field and Register
Pending processor access
PrAcc field in the EJTAG Control register
Read or write access
PRnW field in the EJTAG Control register
Size and data location
Psz field in EJTAG Control register, and two or three LSBs in
the Address register
Address
Address register
Data
Data register
Table 20.52 Information Provided to Probe at Processor Access